LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 117

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

7.3.1
7.3.2
7.3.3
7.3.4
June 14, 2007
Timing” on page 114). The registers that require a delay are denoted with a footnote in
Table 7-1 on page 118.
Initialization
The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal
is used, perform the following steps:
1.
2.
If a 32.678-kHz oscillator is used, then perform the following steps:
1.
2.
The above is only necessary when the entire system is initialized for the first time. If the processor
is powered due to a wake from hibernation, then the Hibernation module has already been powered
up and the above steps are not necessary. The software can detect that the Hibernation module
and clock are already powered by examining the CLK32EN bit of the HIBCTL register.
RTC Match Functionality (No Hibernation)
The following steps are needed to use the RTC match functionality of the Hibernation module:
1.
2.
3.
4.
RTC Match/Wake-Up from Hibernation
The following steps are needed to use the RTC match and wake-up functionality of the Hibernation
module:
1.
2.
3.
4.
External Wake-Up from Hibernation
The following steps are needed to use the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128
input path.
Wait for a time of t
other operations with the Hibernation module.
Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input.
No delay is necessary.
Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008.
Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the
HIBIM register at offset 0x014.
Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting.
Write the required RTC match value to the RTCMn registers at offset 0x004 or 0x008.
Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x130.
Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
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XOSC_SETTLE
for the crystal to power up and stabilize before performing any
LM3S1150 Microcontroller
117