LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 39

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

3
June 14, 2007
Memory Map
The memory map for the LM3S1150 controller is provided in Table 3-1 on page 39.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Note:
Table 3-1. Memory Map
Start
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2400.0000
FiRM Peripherals
0x4000.0000
0x4000.1000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.9000
0x4000.A000
0x4000.C000
0x4000.D000
0x4000.E000
0x4000.F000
0x4001.0000
Peripherals
0x4002.0000
0x4002.0800
0x4002.2000
0x4002.4000
0x4002.5000
0x4002.6000
0x4002.7000
0x4002.8000
0x4002.9000
In Table 3-1 on page 39 addresses not listed are reserved.
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End
0x1FFF.FFFF
0x200F.FFFF
0x21FF.FFFF
0x23FF.FFFF
0x3FFF.FFFF
0x4000.0FFF
0x4000.3FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.9FFF
0x4000.BFFF
0x4000.CFFF
0x4000.DFFF
0x4000.EFFF
0x4000.FFFF
0x4001.FFFF
0x4002.07FF
0x4002.0FFF
0x4002.3FFF
0x4002.4FFF
0x4002.5FFF
0x4002.6FFF
0x4002.7FFF
0x4002.8FFF
0x4002.BFFF
a
Description
On-chip flash
Bit-banded on-chip SRAM
Reserved non-bit-banded SRAM space
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
Reserved non-bit-banded SRAM space
Watchdog timer
Reserved
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SSI0
SSI1
Reserved
UART0
UART1
UART2
Reserved
Reserved for future FiRM peripherals
I2C Master 0
I2C Slave 0
Reserved
GPIO Port E
GPIO Port F
GPIO Port G
GPIO Port H
PWM
Reserved
b
c
LM3S1150 Microcontroller
For details
on
registers,
see page ...
135
135
-
131
-
230
-
160
160
160
160
302
302
-
258
258
258
-
-
339
352
-
160
160
160
160
381
-
39