LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 372

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Analog Comparators
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x24
Type R/W, reset 0x0000.0000
372
Reset
Reset
Type
Type
Bit/Field
31:11
10:9
8:5
3:2
4
RO
RO
31
15
0
0
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64
These registers configure the comparator’s input and output.
RO
RO
30
14
0
0
reserved
reserved
ASRCP
ISLVAL
reserved
Name
ISEN
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
0
0
RO
RO
R/W
RO
26
10
0
0
ASRCP
Reset
0
0
0
0
0
R/W
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The ISLVAL bit specifies the sense value of the input that generates
an interrupt if in Level Sense mode. If 0, an interrupt is generated if the
comparator output is Low. Otherwise, an interrupt is generated if the
comparator output is High.
The ISEN field specifies the sense of the comparator output that
generates an interrupt. The sense conditioning is as follows:
RO
RO
ASRCP
00
01
10
11
ISEN
00
01
10
11
24
0
8
0
reserved
Function
Level sense, see ISLVAL
Falling edge
Rising edge
Either edge
RO
RO
23
0
7
0
Function
Pin value
Pin value of C0+
Internal voltage reference
Reserved
reserved
RO
RO
22
0
6
0
RO
RO
21
0
5
0
ISLVAL
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
ISEN
R/W
RO
18
0
2
0
June 14, 2007
CINV
R/W
RO
17
0
1
0
reserved
RO
RO
16
0
0
0