LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 342

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Inter-Integrated Circuit (I
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type R/W, reset 0x0000.0000
342
Reset
Reset
Type
Type
Bit/Field
Bit/Field
31:4
2
1
0
3
2
1
0
RO
RO
31
15
0
0
RO
RO
30
14
0
0
ADRACK
reserved
ERROR
START
Name
BUSY
Name
STOP
ACK
RUN
RO
RO
29
13
0
0
2
C) Interface
Luminary Micro Confidential-Advance Product Information
RO
RO
28
12
0
0
RO
RO
Type
Type
27
11
0
0
RO
W
W
W
W
R
R
R
RO
RO
26
10
0
0
reserved
Reset
Reset
0
0
0
0
0
0
0
0
RO
RO
25
0
9
0
Description
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 14-3 on page 343.
When set, causes the generation of the STOP condition. See field
decoding in Table 14-3 on page 343.
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 14-3 on page 343.
When set, allows the master to send or receive data. See field decoding
in Table 14-3 on page 343.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
ACK
RO
19
W
0
3
0
STOP
RO
18
W
0
2
0
June 14, 2007
START
RO
17
W
0
1
0
RUN
RO
16
W
0
0
0