DSP56F803 Motorola Inc, DSP56F803 Datasheet - Page 9

• Manufacturer Part Number: DSP56F803
• Description: 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

2.4 Address, Data, and Bus Control Signals
56F803 Technical Data
No. of
No. of
Pins
No. of
Pins
Pins
1
16
6
2
8
GPIOA0
GPIOE2
GPIOE3
A8–A15
GPIOA7
Signal
A0–A5
A6–A7
CLKO
Signal
Name
Name
D0–D15
Signal
Name
–
–
Signal
Output
Output
Output
Output
Output
Signal
Output
Input/
Input/
Type
Type
Signal
Output
Input/
Type
Freescale Semiconductor, Inc.
Table 6. PLL and Clock (Continued)
For More Information On This Product,
State During
State During
Chip-driven
Tri-stated
Tri-stated
Tri-stated
State During
Table 7. Address Bus Signals
Reset
Reset
Input
Input
Tri-stated
Table 8. Data Bus Signals
Reset
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Address Bus—A0–A5 specify the address for external Program
or Data memory accesses.
Address Bus—A6–A7 specify the address for external Program
or Data memory accesses.
Port E GPIO—These two pins are General Purpose I/O (GPIO)
pins that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
Port A GPIO—These eight pins are General Purpose I/O (GPIO)
pins that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Data Bus— D0–D15 specify the data for external Program or
Data memory accesses. D0–D15 are tri-stated when the
external bus is inactive. Internal pull-ups may be active.
Signal Description
Signal Description
Address, Data, and Bus Control Signals
Signal Description
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