DSP56F803 Motorola Inc, DSP56F803 Datasheet - Page 18

• Manufacturer Part Number: DSP56F803
• Description: 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

Operating Conditions:
18
Input capacitance
Output capacitance
V
Low Voltage Interrupt, external power supply
Low Voltage Interrupt, internal power supply
Power on Reset
DD
1.
TDI, and MSCAN_RX
2.
3.
4.
5.
6.
configured as inputs; measured with all modules enabled.
7.
no DC loads; less than 50pF on all outputs. C
linearly affects wait I
8.
potential as V
guaranteed under transient conditions when V
V
9.
voltage is regulator drops below V
interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V).
10. Power
power is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long
the ramp-up rate is. The internally regulated voltage is typically 100mV less than V
reached, at which time it self-regulates.
EIO
supply current
Wait
Stop
Run
Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, TCS, TCK, TRST, TMS,
Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
PWM pin output source current measured with 50% duty cycle.
PWM pin output sink current measured with 50% duty cycle.
I
Run (operating) I
Wait I
This low-voltage interrupt monitors the V
This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal
interrupt is generated).
DDT
7
6
= I
DD
–
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While
DD
DD
10
measured using external square wave clock source (f
Characteristic
+ I
via separate traces. If V
Table 22. DC Electrical Characteristics (Continued)
DDA
DD
V
DD
SS
; measured with PLL enabled.
(Total supply current for V
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
= V
Freescale Semiconductor, Inc.
SSA
For More Information On This Product,
EIC
= 0 V, V
, an interrupt is generated. Since the core logic supply is internally regulated, this
DDA
Go to: www.freescale.com
DD
9
drops below V
L
DDA
8
= V
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance
DDA
>V
DDA
DD
external power supply. V
EIO
+ V
= 3.0–3.6 V, T
(between the minimum specified V
DDA
EIO
Symbol
C
I
V
V
V
DDT
C
, an interrupt is generated. Functionality of the device is
)
POR
OUT
EIO
EIC
IN
5
osc
A
= 8MHz) into XTAL; all inputs 0.2V from rail;
= –40 to +85 C, C
DDA
Min
2.4
2.0
—
—
—
—
—
—
is generally connected to the same
DD
during ramp-up, until 2.5V is
L
Typ
126
105
2.7
2.2
1.7
DD
12
60
8
50pF, f
and the point when the
56F803 Technical Data
op
Max
152
129
3.0
2.4
2.0
84
—
—
= 80MHz
Unit
mA
mA
mA
pF
pF
V
V
V