DSP56F803 Motorola Inc, DSP56F803 Datasheet - Page 25

• Manufacturer Part Number: DSP56F803
• Description: 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

Operating Conditions:
3.5.4
Operating Conditions:
56F803 Technical Data
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
PLL stabilization time
Frequency of operation (external clock driver)
Clock Pulse Width
External
1.
correctly. The PLL is optimized for 8MHz input crystal.
2.
in the User Manual. ZCLK = f
3.
Note: The midpoint is V
1.
2.
3.
Clock
ZCLK may not exceed 80MHz. For additional information on ZCLK and f
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
See
The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
Parameters listed are guaranteed by design.
Phase Locked Loop Timing
Figure 11
Table 26. External Clock Operation Timing Requirements
Characteristic
Characteristic
2
10%
50%
90%
,
3
3
3
for details on using the recommended connection of an external clock driver.
2
-40
0
V
V
o
SS
SS
t
o
to +85
PW
IL
to 0
= V
= V
+ (V
Freescale Semiconductor, Inc.
op
SSA
SSA
o
For More Information On This Product,
o
C
IH
C
Figure 12. External Clock Timing
= 0 V, V
= 0 V, V
– V
IL
)/2.
Table 27. PLL Timing
Go to: www.freescale.com
DD
DD
= V
= V
t
1
PW
1
DDA
DDA
f
t
Symbol
osc
PW
= 3.0–3.6 V, T
= 3.0–3.6 V, T
Symbol
f
f
out
t
t
osc
plls
plls
/2
A
A
6.25
Min
= –40 to +85 C
= –40 to +85 C
0
Min
40
—
—
4
out
/2, please refer to the OCCS chapter
Typ
—
—
Typ
100
—
8
1
External Clock Operation
Max
Max
110
200
80
—
10
10
3
10%
50%
90%
V
V
MHz
Unit
Unit
MHz
MHz
IH
IL
ns
ms
ms
25