DSP56F803 Motorola Inc, DSP56F803 Datasheet - Page 14

• Manufacturer Part Number: DSP56F803
• Description: 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

2.11 Analog-to-Digital Converter (ADC) Signals
2.12 Quad Timer Module Signals
2.13 JTAG/OnCE
14
No. of
No. of Pins
No. of
Pins
Pins
1
1
1
1
1
1
4
4
1
2
Signal
Name
TRST
TCK
TMS
TDO
ANA0
ANA4
TDI
DE
Signal
Name
VREF
Signal Name
–
–
3
7
(Schmitt)
(Schmitt)
(Schmitt)
(Schmitt)
Table 18. JTAG/On-Chip Emulation (OnCE) Signals
TD1
Signal
Output
Output
Type
Input
Input
Input
Input
Table 16. Analog to Digital Converter Signals
–
Signal
Type
Input
Input
Input
2
Freescale Semiconductor, Inc.
Table 17. Quad Timer Module Signals
Input, pulled low
For More Information On This Product,
high internally
high internally
high internally
State During
Input, pulled
Input, pulled
Input, pulled
Tri-stated
internally
State During
Output
Reset
Signal Type
Input/Output
Reset
Input
Input
Input
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Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
Test Mode Select Input—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Test Data Input—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
Test Data Output—This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
Test Reset—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted at power-up and whenever
RESET is asserted. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
Debug Event—DE provides a low pulse on recognized debug
events.
ANA0
ANA4
VREF—Analog reference voltage for ADC. Must be set to
V
DDA
State During Reset
-0.3V for optimal performance.
–
–
3—Analog inputs to ADC channel 1
7—Analog inputs to ADC channel 2
Input
Signal Description
Signal Description
TD1
–
2— Timer D Channel 1
Signal Description
56F803 Technical Data
–
2