DSP56F803 Motorola Inc, DSP56F803 Datasheet - Page 28

• Manufacturer Part Number: DSP56F803
• Description: 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

Operating Conditions:
28
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Table 29. Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)
1.
2.
3.
This is not the minimum required so that the IRQA interrupt is accepted.
4.
5.
A0–A15,
D0–D15
RD, WR
PS, DS,
IRQA,
IRQB
RESET
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
The interrupt instruction fetch is visible on the pins only in Mode 3.
Parameters listed are guaranteed by design.
Figure 15. External Interrupt Timing (Negative-Edge-Sensitive)
Characteristic
t
RAZ
V
SS
= V
Figure 14. Asynchronous Reset Timing
Freescale Semiconductor, Inc.
SSA
For More Information On This Product,
= 0 V, V
DD
Go to: www.freescale.com
= V
t
RA
t
IRW
DDA
= 3.0–3.6V, T
Symbol
t
IRQ
t
t
IF
II
A
= –40 to +85 C, C
Min
—
—
—
—
—
—
275,000T
275,000T
275,000T
L
Max
12T
12T
12T
50pF
56F803 Technical Data
t
RDA
First Fetch
First Fetch
Unit
ns
ns
ns
ns
ns
ns
Figure 18
Figure 19
Figure 19
Figure
See
1, 5