HM-6504 Intersil Corporation, HM-6504 Datasheet - Page 8

• Manufacturer Part Number: HM-6504
• Description: 4096 x 1 CMOS RAM
• Manufacturer: Intersil Corporation

Timing Waveforms
The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.
Recall that in the early write, the output is guaranteed to
remain high impedance, and in the read-modify-write, the
output is guaranteed valid at access time. The late write is
REFERENCE
REFERENCE
TIME
-1
0
1
2
3
4
5
TIME
W
Q
A
D
E
H
H
E
L
L
(Continued)
HIGH Z
-1
TEHEL
(6)
TAVEL
W
X
H
H
H
X
H
ADD VALID
(7)
INPUTS
0
TDVWL
(14)
TELQX
FIGURE 3. LATE WRITE CYCLE
A
X
V
X
X
X
X
V
(3)
HM-6504/883
DATA VALID
TELAX
TRUTH TABLE
(8)
D
X
X
V
X
X
X
X
1
6-141
(5) TELEH
between these two cases. With this cycle the output may
become active, and may become valid data, or may remain
active but undefined. Valid data is written into the RAM if
data setup, data hold, write setup and write pulse widths are
observed.
TWLWH
OUTPUTS
(9)
TWLDX
(18) TELEL
Q
Z
Z
X
X
X
Z
Z
(16)
TWLEH
(10)
Memory Disabled
Cycle Begins, Addresses are Latched
Write Begins, Data is Latched
Write In Progress Internally
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
2
3
TEHQZ
(4)
TEHEL
FUNCTION
(6)
4
TAVEL
(7)
NEXT ADD
5
HIGH Z