HM-6504 Intersil Corporation, HM-6504 Datasheet - Page 2

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HM-6504

Manufacturer Part Number
HM-6504
Description
4096 x 1 CMOS RAM
Manufacturer
Intersil Corporation
Datasheet
Functional Diagram
NOTES:
1. All lines active high-positive logic.
2. Three-state Buffers: A high
3. Control and Data Latches: L low
4. Address Latches: Latch on falling edge of E.
5. Gated Decoders: Gate on rising edge of G.
LSB
A8
A7
A6
A0
A1
A2
W
D
E
output active.
REGISTER
ADDRESS
LATCHED
Q = D and Q latches on rising edge of L.
L
D
D
LATCH
LATCH
L
L
A
A
6
6
Q
Q
D
DECODER
GATED
LATCH
ROW
HM-6504/883
G
L
Q
6-135
64
A
LSB A11 A5 A4 A3 A9 A10
G
L
GATED COLUMN
DECODER AND
6
A
REGISTER
ADDRESS
LATCHED
DATA I/O
MATRIX
64 x 64
64
6
A
D
LATCH
L
Q
A
Q

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