HM-6504 Intersil Corporation, HM-6504 Datasheet - Page 7

• Manufacturer Part Number: HM-6504
• Description: 4096 x 1 CMOS RAM
• Manufacturer: Intersil Corporation

Timing Waveforms
The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of E
(T = 0), the addresses, the write signal, and the data input
are latched in on-chip registers. The logic value of W at the
time E falls determines the state of the output buffer for that
cycle. Since W is low when E falls, the output buffer is
latched into the high impedance state and will remain in that
TIME REFERENCE
REFERENCE
-1
0
1
2
3
4
TIME
W
Q
A
E
D
HIGH-Z
H
H
E
L
TEHEL
-1
(Continued)
(6)
TWLEL
TAVEL
TDVEL
(11)
(15)
(7)
DATA VALID
ADD VALID
0
W
X
X
X
X
L
L
TELWH
TELDX
TELAX
INPUTS
(13)
(17)
(8)
FIGURE 2. EARLY WRITE CYCLE
A
X
V
X
X
X
V
HM-6504/883
TRUTH TABLE
D
X
V
X
X
X
V
6-140
state until E returns high (T = 2). For this cycle, the data
input is latched by E going low; therefore, data set up and
hold times should be referenced to E. When E (T = 2)
returns to the high state, the output buffer and all inputs are
disabled and all signals are unlatched. The device is now
ready for the next cycle.
(5) TELEH
OUTPUT
Q
Z
Z
Z
Z
Z
Z
(18) TELEL
1
Memory Disabled
Cycle Begins, Addresses are Latched
Write in Progress Internally
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
FUNCTION
2
(6) TEHEL
3
TWLEL
TAVEL
TDVEL
NEXT DATA
(11)
(15)
(7)
NEXT ADD
HIGH-Z
4