HM-6561 Intersil Corporation, HM-6561 Datasheet
HM-6561
Related parts for HM-6561
HM-6561 Summary of contents
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... Copyright HM-6561/883 Description The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high per- formance and low power operation. On-chip latches are provided for address and data outputs allowing effi ...
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... S1 S2 NOTES: 1. All lines positive logic-active high. 2. Three-state Buffers: A high output active. 3. Data Latches: L high and Q latches on falling edge Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E. HM-6561/883 A LATCHED GATED 5 ADDRESS ROW 32 REGISTER ...
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... Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55 Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V TABLE 1. HM-6561/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL Output Low Voltage ...
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... TABLE 2. HM-6561/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS Chip Enable (1) TELQV VCC = 4.5 and Access Time 5.5V Address Access (2) TAVQV VCC = 4.5 and Time 5.5V, (Note 3) Chip Select (3) TSLQX VCC = 4.5 and Output Enable 5.5V Time Chip Select (4) TSHQZ VCC = 4.5 and Output Disable 5 ...
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... TABLE 3. HM-6561/883 ELECTRICAL PERFORMANCE SPECIFICATIONS SYMBOL PARAMETER CI Input Capacitance VCC = Open 1MHz, All Measurements Referenced to Device Ground CO Output Capacitance VCC = Open 1MHz, All Measurements Referenced to Device Ground NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes ...
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... X NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either are high. The HM-6561/883 Read Cycle is initiated on the falling edge of E. This signal latches the input address word into on-chip registers. Minimum address setup and hold times must be met ...
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... Data input/output multiplexing is controlled by W. Care must be taken to avoid data bus conflicts, where the RAM outputs become enabled when another device is driving the data inputs. The following two examples illustrate the timing required to avoid bus conflicts. HM-6561/883 (8) TELAX VALID (17) TELEL ...
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... Case 2. Read-Modify-Write cycles and Read-Write-Read cycles can IGNORE be performed (extension of Case 1). In fact data may be modified as many times as desired with E remaining low. TWLQZ TWLWH TWLDV TDVWH TWLWH TWLQZ TDVWH TWLDV HM-6561/883 CERDIP VCC 1 A3 VCC ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HM-6561/883 WORST CASE CURRENT DENSITY: 5 1.337 x 10 A/cm LEAD TEMPERATURE (10s soldering): o 300 C HM-6561/883 6-125 2 DQ3 DQ2 DQ1 DQ0 S2 ...