HM-6504 Intersil Corporation, HM-6504 Datasheet - Page 6

• Manufacturer Part Number: HM-6504
• Description: 4096 x 1 CMOS RAM
• Manufacturer: Intersil Corporation

Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
REFERENCE
TIME REFERENCE
TIME
W
Q
A
E
-1
0
1
2
3
4
5
HIGH Z
HIGH
TEHEL
-1
(6)
TAVEL
E
H
H
L
L
(7)
ADD VALID
0
TELQX
TELAX
INPUTS
(3)
(8)
(1) TELQV
W
H
H
H
H
H
X
X
1
FIGURE 1. READ CYCLE
A
X
V
X
X
X
X
V
HM-6504/883
TRUTH TABLE
6-139
OUTPUT
enabled but the data is not valid until during time (T = 2). W
must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all input, and ready the RAM for the
next memory cycle (T = 4).
TELEH
Q
X
V
V
Z
Z
Z
Z
(5)
TELEL (18)
VALID DATA OUTPUT
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
2
(4) TEHQZ
FUNCTION
3
TEHEL
4
(6)
TAVEL
NEXT ADD
(7)
HIGH Z
5