HM-65642 Intersil Corporation, HM-65642 Datasheet

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HM-65642

Manufacturer Part Number
HM-65642
Description
8k X 8 Asynchronous Cmos Static Ram
Manufacturer
Intersil Corporation
Datasheet
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• This Circuit is Processed in Accordance to MIL-STD-
• Full CMOS Design
• Six Transistor Memory Cell
• Low Standby Supply Current . . . . . . . . . . . . . . . .100 A
• Low Operating Supply Current . . . . . . . . . . . . . . . 20mA
• Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
• Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
• Equal Cycle and Access Times
• No Clocks or Strobes Required
• Gated Inputs
• Temperature Range -55
• Easy Microprocessor Interfacing
• Dual Chip Enable Control
Ordering Information
Pinouts
CERDIP
CLCC
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
- No Pull-Up or Pull-Down Resistors Required
GND
DQ0
DQ1
DQ2
A12
NC
A7
A6
A5
A4
A3
A2
A1
A0
PACKAGE
10
11
12
13
14
1
2
3
4
5
6
7
8
9
HM-65642/883 (CERDIP)
TOP VIEW
TEMPERATURE RANGE
-55
-55
o
o
o
C to +125
|
C to +125
C to +125
Copyright
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
o
o
o
©
C
C
C
Intersil Corporation 1999
DQ0
HM1-65642B/883
HM4-65642B/883
NC
A6
A5
A4
A3
A2
A1
A0
150ns/75 A
10
12
13
11
5
6
7
8
9
14 15
4
HM4-65642/883 (CLCC)
HM-65642/883
3
6-220
TOP VIEW
16 17 18 19 20
2
Description
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simplified by the convenient output enable (G)
input.
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili-
tary temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices
1
HM1-65642/883
HM4-65642/883
32 31 30
150ns/150 A
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
G
A10
E1
DQ7
DQ6
HM1-65642C/883
200ns/250 A
8K x 8 Asynchronous
GND
VCC
PIN
DQ
NC
E1
E2
-
W
CMOS Static RAM
A
G
File Number
Address Input
Data Input/Output
Chip Enable
Chip Enable
Write Enable
Output Enable
No Connections
Ground
Power
DESCRIPTION
F28.6
J32.A
PKG. NO.
3004.1

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HM-65642 Summary of contents

Page 1

... Intersil 80C86 and 80C88 micropro- cessors is simplified by the convenient output enable (G) input. The HM-65642/883 is a full CMOS RAM which utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full mili- tary temperature range ...

Page 2

... Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55 Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL High Level Output VOH 1 VCC = 4 ...

Page 3

... TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested PARAMETER SYMBOL Data Retention ICCDR HM-65642B/883 Supply Current VCC = 2.0V VCC -0. GND +0.3V HM-65642/883 VCC = 2.0V VCC -0. GND +0.3V HM-65642C/883 VCC = 2.0V VCC -0. GND +0.3V Functional Test FT VCC = 4.5V (Note 3) NOTES: 1. All voltages referenced to device GND. ...

Page 4

... TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) (NOTES 1, 2) PARAMETERS SYMBOL CONDITIONS Data Hold Time TWHDX VCC = 4.5V and 5.5V TE1HDX VCC = 4.5V and 5.5V TE2LDX VCC = 4.5V and 5.5V NOTES: 1. All voltages referenced to device GND measurements assume transition time 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load and CL 50pF, for CL > ...

Page 5

... HM-65642/883 TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS GROUPS METHOD Interim Test 1 100%/5004 Interim Test 100%/5004 PDA 100%/5004 Final Test 1 100%/5004 Group A Samples/5005 Groups C and D Samples/5005 SUBGROUPS - 8A, 8B, 10 8A, 8B 6-224 ...

Page 6

... G TGLQV TGLQX Q HM-65642/883 1. The RAM must be kept disabled during data retention. This is ac- complished by holding the E2 pin between -0.3V and GND. 2. During power-up and power-down transitions, E2 must be held between -0.3V and 10% of VCC. 3. The RAM can begin operating one TAVAX after VCC reaches the minimum operating voltage of 4 ...

Page 7

... FIGURE 5. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx A xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx TAVE2H xxxxx xxxxx W xxxxx xxxxx xxxxx E1 xxxxx E2 D FIGURE 6. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2 HM-65642/883 TAVAX TWLWH TDVWH TWLQZ FIGURE 4. WRITE CYCLE I: LATE WRITE TAVAX TE1LE1H TDVE1H TAVAX TE2HE2L TDVE2L 6-226 TWHAX xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx ...

Page 8

... DQ7 DQ0 DQ6 DQ5 17 F2 DQ4 16 F2 DQ3 15 F2 NOTES 100kHz 10 0.01 F Min. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. 6-227 IOL HM-65642/883 CLCC TOP VIEW A11 A10 ...

Page 9

... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HM-65642/883 GLASSIVATION: Type: SiO 2 Thickness: 8k WORST CASE CURRENT DENSITY A/cm HM-65642/883 VCC W GND DQ3 DQ4 DQ5 6-228 Å Å 1k ...

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