HM-6551 Intersil Corporation, HM-6551 Datasheet
HM-6551
Related parts for HM-6551
HM-6551 Summary of contents
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... Copyright HM-6551/883 Description The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous cir- cuit design techniques are employed to achieve high perfor- mance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems ...
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... and Q latches on rising edge Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge All lines positive logic-active high. 4. Three-State Buffers: A high output active. 5. Data Latches: L High and Q latches on falling edge of L. HM-6551/883 5 GATED ROW 32 MATRIX ...
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... Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55 Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V TABLE 1. HM-6551/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL Output Low Voltage VOL VCC = 4 ...
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... TABLE 2. HM-6551/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS Chip Enable (1) TELQV VCC = 4.5 and Access Time 5.5V Address Access (2) TAVQV VCC = 4.5 and Time 5.5V, Note 3 Chip Select 1 (3) TS1LQX VCC = 4.5 and Output Enable 5.5V Time Write Enable (4) TWLQZ VCC = 4 ...
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... TABLE 3. HM-6551B/883 AND HM-6551/883 ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL Input Capacitance CI VCC = Open 1MHz, All Measurements Referenced to Device Ground Output Capacitance CO VCC = Open 1MHz, All Measurements Referenced to Device Ground NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes ...
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... The HM-6551/883 Read Cycle is initiated by the falling edge of E. This signal latches the input address word and S2 into on-chip registers providing the minimum setup and hold times are met. After the required hold time, these inputs may change state without affecting device operation. S2 acts as a high order address and simplifi ...
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... Data may be modified an indefinite number of times during any write cycle (TELEH). The HM-6551/883 may be used on a common I/O bus struc- ture by tying the input and output pins together. The multiplex- ing is accomplished internally by the W line. In the write cycle, when W goes low, the output buffers are forced to a high impedance state ...
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... F10 F11 NOTES: All resistors 47k 5 100kHz 10 F12 = F11 VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V 0.01 F Min. HM-6551/883 + IOH 1.5V - EQUIVALENT CIRCUIT HM-6551/883 CERDIP VCC C1 1 VCC ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HM-6551/883 WORST CASE CURRENT DENSITY: 5 1.337 x 10 A/cm LEAD TEMPERATURE (10s soldering): o 300 C HM-6551/883 6-109 ...