VT6516 ETC, VT6516 Datasheet - Page 58

• Manufacturer Part Number: VT6516
• Description: 16/12 PORT 10/1000 ASE T/TX
• Manufacturer: ETC

30H
31H
32H
33H
34H
35H
20H
21H
40H
Write packet command
3’b100 : end of frame with the remaining data size = 2 bytes
3’b101 : end of frame with the remaining data size = 1 byte
3’b000 : idle
3’b001 : start of frame for the next write
3’b010 : middle of frame for the next write
3’b011 : abort the unfinished packet write
CPU should write this command register before repeatedly writing
8/16 bit packet data VIA the ISA/IDE bus (with a2, a1, a0 = 000).
Packet Abort
Write this register to drop an incoming packet ready to be read by
CPU.
bits [47:40] of switch base MAC address [47:0]
Each port in the switch IC has a unique MAC address with the port
ID as address bits [3:0] and the same MAC base bits [47:4],
specified by the register SWITCH_MAC_BASE[47:4].
bits [39:32] of switch base MAC address [47:0]
bits [31:24] of switch base MAC address [47:0]
bits [23:16] of switch base MAC address [47:0]
bits [15:8] of switch base MAC address [47:0]
bits [7:4] of switch base MAC address [47:0]
interrupt mask register
bit 0: PHY interrupt mask
bit 1: EEPROM interrupt mask
bit 2: packet received interrupt mask
bit 3: packet sent interrupt mask
The four interrupts can be masked individually. The value 0
indicates “Masked”, and value 1 (default) indicates “Unmasked”.
VIA Technologies, Inc.
(that is the low byte as using 16-bit write)
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Preliminary VT6516 Datarsheet
WR_PKT_
CMD
ERR_ABO
RT
SWITCH_
MAC_BA
SE
SWITCH_
MAC_BA
SE
SWITCH_
MAC_BA
SE
SWITCH_
MAC_BA
SE
SWITCH_
MAC_BA
SE
SWITCH_
MAC_BA
SE
IRQSTS_
MASK
[2:0]
[0]
[7:0] 0
[7:0] 0
[7:0] 0
[7:0] 0
[7:0] 0
[7:4] 0
[3:0] 4’b11
11
W/
O
W/
O
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W