VT6516 ETC, VT6516 Datasheet - Page 33

• Manufacturer Part Number: VT6516
• Description: 16/12 PORT 10/1000 ASE T/TX
• Manufacturer: ETC

VIA Technologies, Inc.
Preliminary VT6516 Datarsheet
4. F
D
UNCTIONAL
ESCRIPTION
4.1 Packet Reception and Address recognition
When VT6516 received frames from network, the input control module will receive packet from input MAC
module, then get the output port mask from forwarding table control module, request packet buffer from buffer
control, write packet from input FIFO to packet buffer scheduled by scheduler module, queue packet to the
output queue through queue control module. And update the forwarding table by the source address of the
received good packet.
Usually the source MAC address will be learned and stored to forwarding table. If VLAN is configured by user,
the frame tag type and VLAN ID will also be learned. The source MAC address bit 47~11 and VLAN ID will be
record in the forwarding table entry indexed by source MAC address bit 10~0 or 14~0.
The on chip multicast forwarding configuration registers mainly are for well-known addresses which are listened
by CPU. External multicast addresses are for dynamically assigned. Also some static Mac addresses/port mask
registers can be configured by CPU, these addresses will also be checked before look up the forward table.
4.2 Packet Forwarding and VLAN
The VT6516’s queue control maintains all head and tail pointers for all output ports. Accept the request to
queue and dequeue packets from input and output control.
Both queue and dequeue operations take only 1 SRAM access (3 words = 96 bits), because the tail node is
stored in the internal register of the queue control
Usually, queue and dequeue operations to a specific output queue can be performed simultaneously. However,
mutual exclusion is applied while only one node in this queue
Each port will maintain a packet counter, it increments when packet gets queued through the tail pointer, it
decrements when packet de-queued through head pointer. The congestion factor is the queued packet count
divided by port media speed. The congestion factor will be used for flow control and multicast, congestion
factor should be roughly equal to the time it takes to transmit all the queued packets.
For multicast packet, based on congestion factor, the least congested output port will be queued first. The
output control will queue the packet to next least congested output port when it is transmitted, the CPU port will
always be last port to be transmitted if the corresponding CPU bit is set in the port mask.
The port speed will be used for cut through forwarding decision. If the packet length is 7ff, it implies the input
control try to cut through, queue control will accept or reject by looking whether the input port speed is equal to
the output port speed and the output don’t have queued packets and any pending transmission. The faster
output port (than input port speed) and CPU port is not able to cut through
Broadcast packet, multicast and look up miss packet will forward(multicast) to those ports which is configured
by software, but default(dump switching hub) will be all ports(or all ports in that VLAN if VLAN is
implemented) except CPU port. Broadcast, multicast packet will check the on chip broadcast forwarding
configuration register and multicast forwarding configuration registers first, if multicast address not match any
of the multicast forwarding configuration registers then it will look up the external SRAM forwarding table.
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