VT6516 ETC, VT6516 Datasheet - Page 15

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VT6516

Manufacturer Part Number
VT6516
Description
16/12 PORT 10/1000 ASE T/TX
Manufacturer
ETC
Datasheet
See Ball
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Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
VIA Technologies, Inc.
EEC
EEIO
MDC
MDIO
RCLK50
DCLK
SCLK
HCLK
RESET
SYSLED[26:0
]
I/O
I/O
O
O
O
O
I
I
I
I
Serial EEPROM Interface Clock Output:
EEPROM Device Addressing in the demo board:
PAGE 0 (EEPROM): Device Address = 1010 000 XXXXXXXX
PAGE 1 (EEPROM): Device Address = 1010 001 XXXXXXXX
PAGE 2 (EEPROM): Device Address = 1010 010 XXXXXXXX
PAGE 3 (EEPROM): Device Address = 1010 011 XXXXXXXX
PAGE 4 (SDRAM BANK-0): Device Address = 1010 100 XXXXXXXX
PAGE 5 (SDRAM BANK-1): Device Address = 1010 101 XXXXXXXX
Serial EEPROM Interface Data I/O
Management Interface (MI) Clock Output
Management Interface (MI) Data I/O
Main Reference Clock:
SDRAM Reference Clock:
SRAM Reference Clock
HOST Reference Clock
HCLK is determined by the strapping pins in SYSLED[3:1], i.e. the jump
selection of J1[5-6, 3-4, 1-2]:
J1[OFF,OFF,OFF]
J1[ OFF,OFF, ON]
J1[OFF, ON, OFF]
J1[OFF, ON, ON]
J1[ ON,OFF,OFF]
SYSTEM RESET
SYSTEM Output Pins for LED:
SYSLED[8:0] are connected to pull-up IO PADs for strapping.
SYSLED[25:9] are connected to IO PADs without pull up/down.
All SYSLED[25:0] are
HOST Interface
-15-
Preliminary VT6516 Datarsheet
=> 8MHz
=> 16MHz
=> 25MHz
=> 4MHz
=> 33MHz

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