VT6516 ETC, VT6516 Datasheet - Page 64

• Manufacturer Part Number: VT6516
• Description: 16/12 PORT 10/1000 ASE T/TX
• Manufacturer: ETC

02H
04H
10H
03H
CPU packet read status register
2’b00: idle or packet read in progress
2’b01: packet received successfully
2’b10: packet received with error
Packet source port ID
CPU can check the incoming packet’s source port
ID VIA the 3-bit register PKT_SRC_PORT before
starting to read it. It is useful to the spanning tree
algorithm.
CPU IO port configuration register
bit 0 : input port enable , 1: input enable, 0: input disable
bit 1 : output port enable , 1: output enable, 0: output disable
CPU packet write status register
bits [1:0] : packet write status
bit 2: CPU Input Control is ready for CPU to write packets
VIA Technologies, Inc.
(It can be ready only after setting CPUIO_CFG[0] = 1.)
(CPU needs to read the same packet again)
0: not ready (default)
1: ready
2’b00: idle or packet write in progress
2’b01: CPU sent packet successfully
2’b10: CPU sent packet unsuccessfully
(CPU needs to re-write the packet again)
-64-
Preliminary VT6516 Datarsheet
RD_PKT_
STATUS
PKT_SRC
_PORT
CPUIO_C
FG
WR_PKT_
STATUS
[1:0] 0
[3:0] 0
[1:0] 0
[2:0] 0
R/O
R/O
R/
W
R/O