VT6516 ETC, VT6516 Datasheet - Page 18

• Manufacturer Part Number: VT6516
• Description: 16/12 PORT 10/1000 ASE T/TX
• Manufacturer: ETC

J
Jumper
HOST Clock
J1 [5-6], [3-4], [1-
2]
PHY Mode
J1 [7-8]
SRAM Type
J1 [11-12,9-10]
RMII interface
Power Supply & Ground
See Ball
See Ball
See Ball
See Ball
See Ball
See Ball
See Ball
See Ball
UMPER
Table
Table
Table
Table
Table
Table
Table
Table
VIA Technologies, Inc.
S
CRS_DV[15:0
]
RXD0[15:0]
RXD1[15:0]
TXEN[15:0]
TXD0[15:0]
TXD1[15:0]
VDD, VDDA
VSS, VSSA
TRAPPING
Pin
SYSLED[3:
1]
SYSLED[4] PHY Device Selection:
SYSLED[6:
5]
I
I
I
O
O
O
P
G
Description
HOST Clock (HCLK) Rate Selection:
J1[OFF,OFF,OFF] (SYSLED[3:1]==3’b111)
J1[ OFF,OFF, ON] (SYSLED[3:1]==3’b110)
J1[OFF, ON, OFF] (SYSLED[3:1]==3’b101)
J1[OFF, ON, ON] (SYSLED[3:1]==3’b100)
J1[ ON,OFF,OFF] (SYSLED[3:1]==3’b011)
J1[OFF] (SYSLED[4]==1’b1)
J1[ ON] (SYSLED[3:1]==1’b0)
SRAM Device Type Selection:
J1[OFF,OFF] (SYSLED[6:5]==2’b11)
J1[OFF,ON] (SYSLED[6:5]==2’b10)
J1[ON,OFF] (SYSLED[6:5]==2’b01)
Carries sense and data valid from port 15 to port 0 :
Receive data zero from port 15 to port 0 :
Receive data one from port 15 to port 0 :
Transmit enable from port 15 to port 0 :
Transmit data zero from port 15 to port 0 :
Transmit data one from port 15 to port 0 :
Positive 3.3V Supply: Supply power to Internal digital logic, Digital I/O
pads, and TD, TX pads. Double bonding may be required.
Negative Supply: digital ground. Multiple bonding pads are required to
separate core and I/O pads ground.
-18-
Preliminary VT6516 Datarsheet
=> RMII PHY
=> MII PHY
=> 64K x 32 SRAM
=> 128K x 32 SRAM
=> 32K x 32 SRAM
=> 8MHz
=> 16MHz
=> 25MHz
=> 4MHz
=> 33MHz