VT6516 ETC, VT6516 Datasheet - Page 36

• Manufacturer Part Number: VT6516
• Description: 16/12 PORT 10/1000 ASE T/TX
• Manufacturer: ETC

S
1. R
The VT6516 incorporates the required command/status registers and various counters for management
purposes. Although the default values of the control registers are predefined in the usual way, there is still a
requirement for CPU intervention. All registers are defined as 8 bits so that long registers have to be divided into
pieces of 8 bits with the Little-Endian principle, i.e. the lower byte in the lower address. There are only eight
registers that are directly accessible for CPU, called the CPU interface registers. They are located with memory
mapping in the range of 8000H ~ 8007H for the microprocessor 8031 in the evaluation board. The other
registers are called the internal registers that are referenced indirectly by the 16-bit address register with offset
02H ~ 03H in the CPU interface address table. While the 16-bit address register is set to reference to the specific
8-bit internal register, the following read or write operation to the 8-bit data register with offset 01H in the CPU
interface address table will cause the specified internal register to be read or written indirectly. Besides, the
address register will increase by one automatically to facilitate the successive read/write operation. If the internal
register is of size less than 8 bits, the value 0’s is always returned for the vacant register space and any write
operations to them take no effect.
2 CPU I
*Note: register table base = 8000H for the evaluation board.
Description
Packet Data Register
[15:0]
Data Register [7:0]
Address Register [7:0]
Address Register [15:8] R/W
TEST Register 0 [7:0]
TEST Register 1 [7:0]
TEST Register 2 [7:0]
TEST Register 3 [7:0]
ECTION
EGISTER
VIA Technologies, Inc.
NTERFACE
II R
T
ABLES
EGISTER
R
EGISTERS
Type Offset Function
R/W
R/W
R/W
W/O 4H
W/O 5H
W/O 6H
W/O 7H
M
0H
1H
2H
3H
AP
M
AP
According to the strapping mode of packet
read/write data bus, two types are defined for 8-
bit and 16-bit data bus, respectively. For 8-bit
CPU, only the low byte of the Packet Data
Register is used for packet read/write. For 16-bit
CPU, the whole 16-bit Packet Data Register is
used for packet read/write.
The read or write operation to the 8-bit data
register will cause the specified internal register
(referenced by the Address Register) to be read
or written indirectly.
Besides, after the read/write operation, the
Address Register will increase by one
automatically to facilitate the successive
read/write operation.
The low-byte address register for the reference to
an internal register with 16-bit address.
The high-byte address register for the reference
to an internal register.
see the description in TEST Register 3
see the description in TEST Register 3
see the description in TEST Register 3
-36-
Preliminary VT6516 Datarsheet