VT6516 ETC, VT6516 Datasheet - Page 19

• Manufacturer Part Number: VT6516
• Description: 16/12 PORT 10/1000 ASE T/TX
• Manufacturer: ETC

S
1. G
802.3 and IEEE 802.3u network. Each of individual port can be either auto-sensing or manually selected to run
at 10Mbps or 100Mbps speed rate and under full or half duplex mode.
transmitting, and deferring of each individual port, and the MAC controller also provides framing, FCS
checking, error handling, status indication and flow control function.
forward up to 148,810 packets/sec on each Ethernet port. The VT6516 support 12 ports MII or 16 ports RMII
(reduce MII) interface for network interface,
The system CPU can access various registers inside VT6516 through a simple ISA-like CPU interface. The CPU
can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading
the corresponding registers. The CPU can also access the register of external transceiver (PHY) device through
the CPU interface.
support the sniffer function to monitor network traffic in special ports.
2. T
VT6516 provides two methods for packet switching, one is cut-through, another is store-and-forwarding. A
typical packet flow for Ethernet switch is described as follows in 4.5.
2.1 Switch initialization procedures
1.
2.
3.
4.
5.
6.
2.2 Packet Switching Flow
1. After the switch microprocessor activates a port during initialization, the input control of that port pre-
ECTION
The VT6516 is a switch engine chip implementation of a 16 ports 10/100M Ethernet switch system for IEEE
There are sixteen independent MACs within the VT6516 chip. The MAC controller controls the receiving,
The VT6516 10/100M N-way switch port IC is wire-speed performance and low-cost packet switch; it can
The VT6516 used the simple 8/16 bits ISA-like interface to support initiation, expansion and management.
The VT6516 supports new features including port based VLAN , 802.3X flow control, and the VT6516 also
The VT6516 switch engine uses the shared memory architecture. In order to improve the packet latency,
Test all of the on board components except the switch chip or access VIA the switch chip, including UART,
LED, etc.
Switch SDRAM test --- switch chip SDRAM control hardware initialization, configuration, SDRAM size
determination (VIA embedded EEPROM in SDRAM module) and read write test.
Switch SRAM test --- switch chip SDRAM control hardware initialization and read write test. Note that the
SRAM size determination is VIA strapping.
Switch IO registers read write test.
Ethernet PHY registers read write test ---- the CPU read/write to PHY devices will go through PHY
control in switch chip. Although they are outside components, but we test them as part of the switch chip.
Determine link table size; reset free buffer list pointers of bank 0 and 1; initialize free memory block counter.
Note that permanent buffer management is controlled by allocating bit mask. They will be cleared
automatically in the hardware reset or software reset.
allocates one packet buffer from buffer pool. In the beginning, the buffer allocated will be from private buffer
pool, but subsequent buffers may come from either private or public buffer pools.
HE
ENERAL
VIA E
VIA Technologies, Inc.
I F
D
THER
ESCRIPTION
UNCTIONAL
S
WITCH
A
D
RCHITECTURE
ESCRIPTIONS
-19-
Preliminary VT6516 Datarsheet