VT6516 ETC, VT6516 Datasheet
VT6516
Related parts for VT6516
VT6516 Summary of contents
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... VIA Technologies, Inc. VT6516 16/12-P ORT E S THERNET REVISION ‘E’ DATASHEET ISSUE 1: July 31, 1999 VIA Technologies, Inc. Preliminary VT6516 Datasheet 10/100B ASE C WITCH ONTROLLER (Preliminary) 1 -T/TX ...
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... Offices: 1045 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 Online Services: BBS : 886-2-2186408 FTP : FTP.VIA.COM.TW HTTP:WWW.VIA.COM.TW Preliminary VT6516 Datasheet th 8 Floor, No. 533 Chung-Cheng Rd., Hsin-Tien Taipei, Taiwan ROC Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453 –or- WWW.VIATECH.COM 2 R ...
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... Registers of PHY Control Module .............................................................................................. 53 4.7 Registers of EEPROM Control Module ....................................................................................... 55 4.8 Registers of CPU Interface Module............................................................................................. 56 4.9 Registers of MAC/IO Control Module ......................................................................................... 59 4.10 Registers of CPU IO Control Module....................................................................................... 63 SECTION III ELECTRICAL SPECIFICATIONS................................................................................. ............................................................................................................... 65 BSOLUTE AXIMUM ATINGS DC C ............................................................................................................................ 65 HARACTERISTICS AC C ............................................................................................................................ 65 HARACTERISTICS ACKAGE ECHANICAL PECIFICATIONS Preliminary VT6516 Datasheet ............................................................................................ 19 ......................................................................................................... 36 ..................................................................................................... 37 AP ................................................................................................. 73 3 ...
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... Figure 3-1 SRAM......................................................................................................26 Figure 3-2 Free buffer link structure ..........................................................................27 Table 1-0 Free buffer link structure............................................................................27 Figure 3-5 The Address table entries structure +........................................................27 Table 1-1 Address table structure ..............................................................................28 Table 3-1 RMII interface signals................................................................................30 Figure 3-1 RMII timing diagram................................................................................30 Table 3-2 MII interface signals ..................................................................................31 Figure 3-2 MII timing diagram ..................................................................................31 Preliminary VT6516 Datasheet 4 ...
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... H EVERSION ISTORY Reversion Date V0.90 2/18/1999 V0.91 6/2/1999 V0.92 8/23/1999 V0.93 9/9/1999 Preliminary VT6516 Datasheet Reason for change First release version Add D version silicon features modification Add E version silicon features modification Revision according to Weipin’s, Kevin’s, and Ruth’s comments 5 By JeffreyChang JeffreyChang MurphyChen ...
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... Configurable server ports belonging to multiple VLAN groups Support port-based trunking l - Three types of trunk grouping: one trunk group with ports, two trunk groups each with 2 ports - Load balance according to MAC address and port number CPU interface VIA 8/16 bits ISA-like interface l Preliminary VT6516 Datasheet 6 ...
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... Chip initialization, auto-aging and spanning tree algorithm support by firmware - Auto-sensing 10/100M media speed, duplex mode, and flow-control capability by firmware 50MHz internal reference clock rate l 50~100MHz SDRAM clock rate, typically 83MHz l 50~100MHz SSRAM clock rate, typically 83MHz l Single +3.3V supply, 0.3 m standard CMOS technology l 476 ball BGA package l Preliminary VT6516 Datasheet 7 ...
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... 99/12/09 Preliminary VT6516 Datarsheet interface ...
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... RXD0.1 CSDV1 TXD0.1 MDC TXEN1 TXD1.1 RXD0.1 MDIO 99/12/09 Preliminary VT6516 Datarsheet MD5 MD7 MD9 MD11 MD45 MD47 RAS0 MA3 MA7 MD36 MD38 MD40 MD42 MD14 CAS1 MA0 MA4 MA8 ...
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... TXEN7 RXDV7 TXD2_ MDC RXD2_ RXDV8 TXD1_ COL8 TXD3_ RXD2_ MDIO RXD3_ RXD1_ TXEN8 TXD2_ CRS8 99/12/09 Preliminary VT6516 Datarsheet MD36 MD38 MD40 MD42 MD14 CAS1# MA0 MA4 MA8 MD4 MD6 MD8 MD10 MD46 ...
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... IOW INTRQ TCLK[11:0] TXD0[11:0] TXD1[11:0] TXD2[11:0] TXD3[11:0] TXEN[11:0] COL[11:0] CRS[11:0] RXD0[11:0] RXD1[11:0] RXD2[11:0] RXD3[11:0] RCLK[11:0] RXDV[11:0] 16 CRS_DV[15:0] 16 RXD0[15:0] 16 RXD1[15:0] 16 TXEN[15:0] 16 TXD0[15:0] TXD1[15:0] Preliminary VT6516 Datarsheet VT6516 3 16 HOST Interface MII 12 12 Interface Miscellaneous 12 Interface 12 12 RMII Interface 16 ...
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... Table See Ball [1:0] O SWE Table Preliminary VT6516 Datarsheet Description SDRAM Interface SDRAM Data: 64-bit SDRAM data bus. These signals connect directly to the data input/output pins of the SDRAM devices. SDRAM Address Bus: 12-bit SDRAM data bus. These signals connect directly to the address input of the SDRAM devices ...
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... Table See Ball SYSLED[26:0 O Table ] Preliminary VT6516 Datarsheet Serial EEPROM Interface Clock Output: EEPROM Device Addressing in the demo board: PAGE 0 (EEPROM): Device Address = 1010 000 XXXXXXXX PAGE 1 (EEPROM): Device Address = 1010 001 XXXXXXXX PAGE 2 (EEPROM): Device Address = 1010 010 XXXXXXXX PAGE 3 (EEPROM): Device Address = 1010 011 XXXXXXXX ...
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... See Ball TCLK[11:0] I Table Preliminary VT6516 Datarsheet HOST IDE-Interface Address Bus: 3’b000: command the switch that the whole 16-bit data in the HOST data bus HD[15:0] is valid for packet-data read/write. 3’b001: command the switch that only the 8-bit data in the HOST data bus HD[15:0] is valid for internal registers read/write. 3’ ...
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... See Ball RXDV[11:0] I Table Note: Some flat MII input pin when the VT6516 under the RMII application, please use 22 ohm resister pull down, refer to Table XXXX Preliminary VT6516 Datarsheet Transmit Data for Port 0-11: TXD is a bundle of 4 data signals (TXD<3:0>) that shall transition to the TCLK. For each TCLK period in which TXEN is asserted, TXD< ...
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... J1[OFF,OFF] (SYSLED[6:5]==2’b11) J1[OFF,ON] (SYSLED[6:5]==2’b10) J1[ON,OFF] (SYSLED[6:5]==2’b01) Preliminary VT6516 Datarsheet Carries sense and data valid from port 15 to port 0 : Receive data zero from port 15 to port 0 : Receive data one from port 15 to port 0 : Transmit enable from port 15 to port 0 : ...
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... The VT6516 10/100M N-way switch port IC is wire-speed performance and low-cost packet switch; it can forward up to 148,810 packets/sec on each Ethernet port. The VT6516 support 12 ports MII or 16 ports RMII (reduce MII) interface for network interface, The VT6516 used the simple 8/16 bits ISA-like interface to support initiation, expansion and management ...
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... VT6516 provides a 64-bit SDRAM/SGRAM interface for packet buffering and a 32-bit synchronous SRAM (SSRAM) interface for maintaining address table and various link lists. VT6516 uses SDRAM as packet buffers. Each packet buffer is a 1536-byte contiguous memory block in SDRAM, and corresponds to a 12-byte link node data structure in SSRAM ...
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... VIA Technologies, Inc. SRAM 12 bytes/entry Permanent Buffer 128 entries Table 12 bytes/entry Free List Link Table Address Table Entriers Preliminary VT6516 Datarsheet DRAM 1.5 K/Packet ... 1.5 K/Packet -21- 128 blocks ...
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... SRAM_CMD_REG 0x2008 #define SRAM_STATUS_REG 0x2009 #define SRAM_ACCESS_IDLE 0x01 #define NULL_PTR 0x7FFFF void writeLinkEntry(int entryID, int nextID) { reg_byte_write (SRAM_ADDR_REG0, entryID*3 & 0x0FF); reg_byte_cont_write (((entryID*3) >> 8) & 0x0FF); reg_byte_cont_write (((entryID*3) >> 16) & 0x0FF); Preliminary VT6516 Datarsheet Links/ Memory Bank List 128/0 Bank 0 4K 129/0 Bank 1 130/0 ...
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... SDRAM, // Bank0 free list head pointer = 128 // Bank1 free list head pointer = 131 int current free entry id int b0, b1; // b0, b1: bank0/1 free list head entry id for(b0=b1= NULL_PTR, k= maxLinkEntryNo; k <=128; k--) if ((( 16) < writeLinkEntry(b0,k); b0=k;} else { writeLinkEntry(b1,k); b1=k;} } Preliminary VT6516 Datarsheet -23- ...
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... In order to provide the cost effective DRAM buffers, user can connect the 32 bits data SGRAM with VT6516 switch, there are two external buffer device using two double bank 128Kbits by 32 required. The following figure shows the minimum configuration of buffer memory and link/address memory. Note that the SGRAM physical memory hole is to accommodate the forwarding table into the SRAM link list hole ...
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... VIA Technologies, Inc. The detail initial step of VT6516 as following, 1. Forwarding table base = 683 * 3 2. SDRAM type equal to 16M bit 3. END0 (16MB) 4. Free list of SRAM have to be constructed by release public node in the sequence of buffers with blocks number 10922, 10911, … . 10240, 681, 680, 128 Note: The buffers numbered 682 to 10239 are located in the buffer memory hole, those buffers will be not put into the free list ...
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... SRAM interface The feature 3-1 is SSRAM structure map, the SSRAM contains the forwarding address entries, SDRAM buffers link list and permanent buffers table. Low Link table Entries * 12 bytes/entry (FREECNT(1006H) * 1.5K) High Preliminary VT6516 Datarsheet 0 Permanent Link Table 16 ports * bytes/entry Link Table Forwarding Table ...
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... Configure port mask register (USER_PM) for broadcast MAC address. Configure port mask and MAC address pairs that allow any static MAC to port mask mapping. Forwarding table entry has 96 bits, defined as follows: Preliminary VT6516 Datarsheet ...
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... CPU interface The VT6516 support one ISA-like CPU interface, this CPU interface can cooperate with one simple microprocessor like 8031 or 8051. The CPU will access the switch control and status register to perform initialization and configurations. By the CPU interface, the frames of CPU port can be read/written from/into the buffer ...
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... VIA Technologies, Inc. - Receiving the STP defined BPDU packets - Blocking or re-start port due to STP - Access the network management counter of each port For a management switch the CPU also perform the management function like receiving and transmitting the SNMP frame. Preliminary VT6516 Datarsheet -29- ...
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... VIA Technologies, Inc. 3.1.4 Network interface The VT6516 directly connect to 16 port RMII PHY or 12 port MII PHY device which compliant with IEEE standard (Please see IEEE 802.3u Fast Ethernet standard) . Each Fast Ethernet port has following characteristics: - Capable of supporting both 10MBps and 100MBps data rates in half and full duplex modes. ...
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... The VT6516 communicates with the external 10/100M Ethernet transceiver through standard MII interface, in this mode the VT6516 became 12 ports MII port due to the MII signal multiplexed with RMII signal. But the ports number of internal remained as 16 ports. The signals of MII interface are described in Table-3-2: 3 ...
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... SMI interface The VT6516 communicates with the external 10/100M PHY and access the PHY register through MDC, MDIO 3.1.4.5 Auto negotiation The VT6516 communicates with the external 10/100M PHY and access the PHY register through MDC, MDIO 3 ...
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... CPU, these addresses will also be checked before look up the forward table. 4.2 Packet Forwarding and VLAN The VT6516’s queue control maintains all head and tail pointers for all output ports. Accept the request to queue and dequeue packets from input and output control. ...
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... Sniffer port The VT6516 support sniffer function for user to monitor the network traffic. The Sniffer port enable can be set for any individual port of sixteen ports. And each sniffer port can set to monitor the traffic coming from any others fifteen port(monitor port). Any packets sent to the monitor ports or transmitted out of monitor port will be forwarded to sniffer port ...
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... VIA Technologies, Inc. Every port of the VT6516 can be set to block and listen mode through the CPU interface. In the mode, incoming frames with DA value equal to the reserved Group address for BPDU will be forward to CPU port and other incoming frames with other DA value will be dropped. Outgoing frames with any DA value will be filtered expect DA equal to BPDU ...
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... EGISTER ABLES The VT6516 incorporates the required command/status registers and various counters for management purposes. Although the default values of the control registers are predefined in the usual way, there is still a requirement for CPU intervention. All registers are defined as 8 bits so that long registers have to be divided into pieces of 8 bits with the Little-Endian principle, i ...
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... CPU Port Speed Configuration 04H 10-13H Congestion Factor of Output Port 0 14-17H Congestion Factor of Output Port 1 18-1BH Congestion Factor of Output Port 2 1C-1FH Congestion Factor of Output Port 3 20-23H Congestion Factor of Output Port 4 Preliminary VT6516 Datarsheet M AP Name Bits Default SDRAMTYPE [0] CL [1:0] 2 RSDM [3:0] 5 END0A [4:0] 0 ...
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... PORT 3 PRIVATE MEMORY ALLOCATION BIT MASK for 14H PORT 4 PRIVATE MEMORY ALLOCATION BIT MASK for 15H PORT 5 PRIVATE MEMORY ALLOCATION BIT MASK for 16H PORT 6 PRIVATE MEMORY ALLOCATION BIT MASK for 17H PORT 7 Preliminary VT6516 Datarsheet CONGEST_FC [25 CONGEST_FC [25 CONGEST_FC [25 CONGEST_FC ...
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... MAC hash address to be aged. 12H aging status 20H spanning tree state for PORT 0 21H spanning tree state for PORT 1 22H spanning tree state for PORT 2 23H spanning tree state for PORT 3 Preliminary VT6516 Datarsheet PORT8_MASK [7:0] 0 PORT9_MASK [7:0] 0 PORT10_MAS [7: PORT11_MAS [7: PORT12_MAS [7: ...
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... VLAN ID 86H port 3 VLAN ID 88H port 4 VLAN ID 8AH port 5 VLAN ID 8CH port 6 VLAN ID 8EH port 7 VLAN ID 90H port 8 VLAN ID 92H port 9 VLAN ID 94H port 10 VLAN ID Preliminary VT6516 Datarsheet PORT4_STP_S [1:0] 0 TATE PORT5_STP_S [1:0] 0 TATE PORT6_STP_S [1:0] 0 TATE PORT7_STP_S [1:0] 0 TATE PORT8_STP_S [1:0] 0 TATE PORT9_STP_S [1:0] 0 ...
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... PORT5 PHY Device Address 16H PORT6 PHY Device Address 17H PORT7 PHY Device Address 18H PORT8 PHY Device Address 19H PORT9 PHY Device Address 1AH PORT10 PHY Device Address Preliminary VT6516 Datarsheet PORT11_VID [5:0] 0 PORT12_VID [5:0] 0 PORT13_VID [5:0] 0 PORT14_VID [5:0] 0 PORT15_VID [5:0] 0 SRV_PM [15:0 ] [0] FG PHYID ...
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... SDRAM status register 20H Write packet command 21H Packet Abort 30H bits [47:40] of switch base MAC address [47:0] 31H bits [39:32] of switch base MAC address [47:0] 32H bits [31:24] of switch base MAC address [47:0] Preliminary VT6516 Datarsheet PORT11_PHY_ [4:0] 0 ADDR PORT12_PHY_ [4:0] 0 ADDR PORT13_PHY_ [4:0] 0 ADDR PORT14_PHY_ [4:0] 0 ADDR PORT15_PHY_ [4:0] 0 ...
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... MAC & I/O Control Module of Port 7 as same as Port 0 4000H MAC & I/O Control Module of Port 8 as same as Port 0 4400H 4800H MAC & I/O Control Module of Port 9 as same as Port 0 4C00H MAC & I/O Control Module of Port 10 Preliminary VT6516 Datarsheet SWITCH_MA [7:0] 0 C_BASE SWITCH_MA [7:0] 0 C_BASE SWITCH_MA [7:4] 0 ...
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... This latency specifies the required delay between the CAS cycle and the first read cycle. Note that the CAS latency has to be specified before using RSDM in SDRAM initialization. Preliminary VT6516 Datarsheet as same as Port 0 as same as Port 0 as same as Port 0 ...
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... END3A = 0CH to indicate the ending address of DIMM Bank 2^26+2^25 (96MB) Bits [27:23] of DIMM Bank 1 Ending Address 04H (see END0A) Bits [27:23] of DIMM Bank 2 Ending Address 05H (see END0A) Bits [27:23] of DIMM Bank 3 Ending Address 06H (see END0A) Preliminary VT6516 Datarsheet RSDM [3:0] END0A [4:0] END1A [4:0] END2A [4:0] END3A [4:0] ...
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... Note: REMEMBER to enable the cut-through function to improve the switching latency. For 100Mbps input port, the smallest latency for cut-through is 288 bytes time (288x8x10 ns). For 10Mbps input port, the smallest latency for cut-through is 96 bytes time (96x8x100 ns). Preliminary VT6516 Datarsheet SDRAM_DR_ [2:0] CFG BK_IL_DIS ...
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... Congestion Factor of Output Port 10 38- 3BH 3C- Congestion Factor of Output Port 11 3FH Congestion Factor of Output Port 12 40- 43H Congestion Factor of Output Port 13 44- 47H 48- Congestion Factor of Output Port 14 4BH Preliminary VT6516 Datarsheet CPU_SPD_CF [2:0] G CONGEST_F [25:0] CT0 CONGEST_F [25:0] CT1 CONGEST_F [25:0] CT2 CONGEST_F [25:0] CT3 ...
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... Read 1006H to get the lowest byte, and also lock the counter information, .i.e. FREEMCNT[7:0] = HD[7:0] (2) Read 0C52H to get the second byte, i.e. FREEMCNT[15:8] = HD[7:0] (3) Read 0C53H to get the FREEMCNT[17:16] FREEMCNT[17:16] = HD[1:0] (4) Read 0C51H to get the FREEMCNT[18] FREEMCNT[18] = HD[7] Preliminary VT6516 Datarsheet CONGEST_F [25:0] CT15 CONGEST_F [25:0] CT16 Register Bits Defau ...
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... PRIVATE MEMORY ALLOCATION BIT MASK for PORT 1CH 12 1DH PRIVATE MEMORY ALLOCATION BIT MASK for PORT 13 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 1EH 14 PRIVATE MEMORY ALLOCATION BIT MASK for PORT 1FH 15 4.5 Registers of Forwarding Control Module Preliminary VT6516 Datarsheet CFP [0] PORT0_M [7:0] 0 ASK PORT1_M [7:0] 0 ASK PORT2_M [7:0] 0 ASK PORT3_M ...
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... CPU 09H The CPU_PM is used as the lookup result for the incoming packets from the CPU port without regard to packet’s DMAC. Preliminary VT6516 Datarsheet Register Bits Defau Name HASH_BITS [2:0] TBL_BASE ...
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... Aging Status 12H 0, idle or done (default) 1: aging in progress After an aging command is issued, the status is recorded in this register. The next age command can only be issued as the status changes from 1 (in-progress (done). Preliminary VT6516 Datarsheet CPU_FWD_C [2:0] FG SNIFFER_PID [3:0] MONITOR_P [16:0] M AGE_MAC ...
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... VLAN ID The VLAN feature is enabled only when all port VID's are configured to a valid (non-zero) VID. port 1 VLAN ID 82H port 2 VLAN ID 84H 86H port 3 VLAN ID port 4 VLAN ID 88H Preliminary VT6516 Datarsheet PORT0_STP_ [1:0] STATE PORT1_STP_ [1:0] STATE PORT2_STP_ [1:0] STATE PORT3_STP_ [1:0] STATE ...
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... CPU is not necessary. The source VID differs from the destination VID. 4.6 Registers of PHY Control Module * Base Address: 1800H Preliminary VT6516 Datarsheet PORT5_VID [5:0] PORT6_VID [5:0] PORT7_VID [5:0] PORT8_VID [5:0] PORT9_VID [5:0] ...
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... In the system initialization, the CPU should write PHY device addresses, corresponding to every PHY devices, to registers PORT[0..15]_PHY_ADDR, that may be recorded in the EEPROM or code ROM. PORT1 PHY Device Address 11H PORT2 PHY Device Address 12H Preliminary VT6516 Datarsheet Register Bits Defau Name PHYID [3:0] 0 PHY_REG [4:0] 0 ...
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... PORT11 PHY Device Address 1BH PORT12 PHY Device Address 1CH 1DH PORT13 PHY Device Address 1EH PORT14 PHY Device Address PORT15 PHY Device Address 1FH 4.7 Registers of EEPROM Control Module * Base Address: 1C00H Preliminary VT6516 Datarsheet PORT3_P [4:0] 0 HY_ADD R PORT4_P [4:0] 0 HY_ADD R PORT5_P [4:0] 0 HY_ADD ...
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... Then, a following “read status” command will cause it back to the “idle” status following read/write command will cause it into the “busy” status. 4.8 Registers of CPU Interface Module * Base Address: 2000H Addres Function s (offset ) Preliminary VT6516 Datarsheet Register Bits Defau Name EEWDAD [7:0] DR EEDATA [7:0] EEDEVA [7:0] ...
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... Read/Write will cause the SDRAMSTS = ”busy” immediately done, SDRAMSTS = “done”. A following read to SDRAMSTS will clear it to “idle”. SDRAM status register 1DH 2’b01 : read/write command done 2’b10 : busy (read/write in progress) 2’b00 : idle Preliminary VT6516 Datarsheet IRQSTS [3:0] 0 SRAMAD [18 SRAMDA ...
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... PHY interrupt mask bit 1: EEPROM interrupt mask bit 2: packet received interrupt mask bit 3: packet sent interrupt mask The four interrupts can be masked individually. The value 0 indicates “Masked”, and value 1 (default) indicates “Unmasked”. Preliminary VT6516 Datarsheet WR_PKT_ [2:0] CMD ERR_ABO [0] ...
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... ICs. 4.9 Registers of MAC/IO Control Module * Base Address: 2400H Addres Function s (offset ) 00H configurable preamble bytes This register specifies the preamble length (0..7 bytes) for outgoing packets. Preliminary VT6516 Datarsheet CPU_SOF [0] T_RESET REVISIO [7:0] 0 N_ID Register Bits Defau Name PREAM_C [2:0] 7 ...
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... Note that, TMAC only performs the carrier sense function during st the 1 IFG interval, rather than the whole IFG. So, for the half duplex link incoming packet arrives at the 2 collision with the ready-to-send outgoing packet will happen. Preliminary VT6516 Datarsheet IFG_CFG [5: interval of the inter- nd IFG interval, a ...
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... For OFSET=1, the TMAC will follow the 802.3 standard backoff algorithm. For OFSET=0, the TMAC will select the backoff time for the 1 collision as that of the 3 the backoff time for the 1 from unit of slot time. Preliminary VT6516 Datarsheet BOFFCFG [4:0] 5’b10 nd collided packet nd collision ...
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... Accounting Event: input FIFO overrun due to SDRAM-bandwidth blocking or buffer starvation. 1CH- sent good packet count 1FH Accounting Event: store-and-forward transmission success without collision Preliminary VT6516 Datarsheet MACCFG [3:0] 0 IO_CFG [1:0] 0 RCV_GO [31:0 OD_PKT ] RCV_BAD [31:0 ...
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... CPU packet read byte count register bits [7:0] CPU can check the incoming packet length VIA the 11-bit register PKT_BYTE_CNT [10:0] before starting to read it. 01H CPU packet read byte count register bits [10:8] Preliminary VT6516 Datarsheet XMT_BA [31:0 D_PKT ] as same as Port 0 as same as Port 0 ...
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... CPU sent packet successfully 2’b10: CPU sent packet unsuccessfully (CPU needs to re-write the packet again) bit 2: CPU Input Control is ready for CPU to write packets (It can be ready only after setting CPUIO_CFG[0] = 1.) 0: not ready (default) 1: ready Preliminary VT6516 Datarsheet RD_PKT_ [1:0] 0 STATUS PKT_SRC [3:0] 0 _PORT ...
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... Input leakage current IL I Tristate leakage current OZ I Power supply current HARACTERISTICS AC timing specifications provided are based on external zero-pf capacitance load. Min/Max cases are based on the following table: Parameter 3.3V power (Vcc) Temperature Preliminary VT6516 Datarsheet S PECIFICATIONS Min 0 0 -55 -0.5 = 3.1 - 3.6V) -0.5 CC Min Max -0.50 0.8 2 ...
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... IOR data setup(read t IORS data valid to IOR rising) t IOR data hold(IOW IORH rising to read data invalid) IOR hhhhhhhhfllllllllllrhhhhhfll ~ ~ t ! VAL HD zzzzznddddddddddddddddozzzzz IOWhhhhhhhhfllllllllllrhhhhhfll ~ ~ t ! VAL HD zzzzznddddddddddddddddozzzzz Preliminary VT6516 Datarsheet MIN IORH ~t !~t ! IORS IORH CPU read timing diagram !~ t t IOWH ...
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... SCLK llrhhhhfllllrhhhhfllllrhhhflllrhhh + ~ t SADS SADS zzzzzndddddddddozzzzzzzzznddddddd + ~ t SCS SCS zzzzzndddddddddozzzzzzzzznddddddd + ~ t SWE SWE zzzzzndddddddddozzzzzzzzznddddddd + ~ zzzzndddddddddozzzzzzzzznddddddd v input cycle + SDS SD nddddozzzzzzzzzzzzzzzzzznddddddo + t ~ SDH Preliminary VT6516 Datarsheet SETUP HOLD MIN 2 2.5 1 turn around cycle v output cycle + -67- MAX UNIT ...
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... DCLK llrhhhhfllllrhhhhfllllrhhhflllrhh + ~ zzzzzndddddddddozzzzzzzzznddddddd + ~ RAS zzzzzndddddddddozzzzzzzzznddddddd + ~ t CAS CAS zzzzzndddddddddozzzzzzzzznddddddd + ~ DWE zzzzzndddddddddozzzzzzzzznddddddd + ~ t DCS DCS zzzzzndddddddddozzzzzzzzznddddddd + ~ zzzzndddddddddozzzzzzzzznddddddd v input cycle + MDS MD nddddozzzzzzzzzzzzzzzzzznddddddo + t ~ NDH Preliminary VT6516 Datarsheet SETUP HOLD MIN 2 1 turn around cycle v output cycle + -68- MAX 6.5 6.5 6.5 6.5 6.5 6 ...
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... TXD TX_EN output t TXD delay lllrhhhhfllllrhhhhfllllrhhhhflll RCLK + RXDS CRS_DVndddddozzzndddddozzznddddddozzzz +t ~ RXDH + RXDS RXD ndddddozzzndddddozzznddddddozzzz +t ~ RXDH + ~ t TXD TX_EN zzzzzndddddddddozzzzzzzzzznddddd + ~ t TXD TXD zzzzzndddddddddozzzzzzzzzznddddd Preliminary VT6516 Datarsheet min type max -69- unit condition RCLK50 rising edge ns to RCLK50 rising edge ns to RCLK50 rising edge ...
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... Management Interface (MI) Timing Characteristics Parameter min MDC cycle time - MDC high time 180 MDC low time 180 MDIO setup time 30 (source by PHY) MDIO hold time 0 (source by PHY) MDIO output 200 Preliminary VT6516 Datarsheet min type - typ max 400 - ...
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... VIA Technologies, Inc. delay (source by vt3061) Preliminary VT6516 Datarsheet -71- edge ...
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... Start Condition setup time Start Condition 6.4 hold time Stop Condition setup time Stop Condition 6.4 hold time Read Data In 0 setup time Read Data In 0 hold time EEIO Data out 2.6 delay Write Cycle time - Preliminary VT6516 Datarsheet typ max 0 78.12 6.4 - 6 ...
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... VIA Technologies, Inc ACKAGE ECHANICAL Preliminary VT6516 Datarsheet PECIFICATIONS -73- ...