VT6516 ETC, VT6516 Datasheet - Page 46
VT6516
Manufacturer Part Number
VT6516
Description
16/12 PORT 10/1000 ASE T/TX
Manufacturer
ETC
Datasheet
1.VT6516.pdf
(73 pages)
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4.2 Registers of SRAM Control Module
* Base Address: 0800H
Addres
s
(offset
)
00H
4.3 Registers of Queue Control Module
* Base Address: 0C00H
Addres
s
(offset
)
00-
02H
03H
07H
08H
SDRAM Command Drive Strength Configure
bit0: RDCSDV --- SDRAM Chip Select Drive Strength
bit1: RMADV --- SDRAM MA drive strength
bit2: RMDDV --- SDRAM MD drive strength
SDRAM Bank Interleaving Disable
0: enable interleaving (default)
1: disable interleaving
Function
SRAM Read Command Interleave Disable
0: enable interleaving (default)
1: disable interleaving
Function
Free Memory Flow Control Threshold register
As FREEMCNT(a register in buffer control) < FMFCT, the
congestion control function will be triggered to command the TMAC
module of the source port, destined to a congested port, to send out
a flow control frame for full duplex mode, or to make back-pressure
for half duplex mode. See the context about congestion control for
details.
Larger the threshold value more sensitive the congestion control
mechanism, i.e. maybe poor utilization for packet buffers but larger
packet loss rate. Smaller the threshold value less sensitive the
congestion control mechanism, i.e. maybe good utilization for
packet buffers but smaller packet loss rate. It depends on the
network configuration and traffic pattern. The recommended
threshold value is 256.
Cut Through Enable
0: Disable Cut Through (default)
1: Enable Cut Through
Note: REMEMBER to enable the cut-through function to improve
the switching latency. For 100Mbps input port, the smallest latency
for cut-through is 288 bytes time (288x8x10 ns). For 10Mbps input
port, the smallest latency for cut-through is 96 bytes time (96x8x100
ns).
VIA Technologies, Inc.
(including RAS,CAS,WE,MA,BA)
-46-
Preliminary VT6516 Datarsheet
SDRAM_DR_
CFG
BK_IL_DIS
Register
Name
SRAM_READ
_IL_DIS
Register
Name
FMFCT
CUT_THROU
GH_EN
[2:0]
[0]
Bits Defau
[0]
Bits Defau
[18:0
]
[0]
0
0
lt
Value
0
lt
Value
0
0
R/W
R/W
R/
W
R/W
R/
W
R/
W
R/W
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