MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 6

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

MT93L00A
Pin Description (continued)
Device Overview
The
cancellers divided into 16 groups. Each group has
two echo cancellers, Echo Canceller A and Echo
Canceller B. Each group can be configured in
Normal,
configurations. In Normal configuration, a group of
echo cancellers provides two channels of 64ms echo
cancellation, which run independently on different
channels. In Extended Delay configuration, a group
of echo cancellers achieves 128ms of echo
cancellation by cascading the two echo cancellers (A
& B). In Back-to-Back configuration, the two echo
cancellers from the same group are positioned to
cancel echo coming from both directions in a single
channel,
cancellation.
Each echo canceller contains the following main
elements (see Figure 3).
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Adaptive Filter for estimating the echo channel
Subtractor for cancelling the echo
Double-Talk detector for disabling the filter
adaptation during periods of double-talk
Path Change detector for fast reconvergence
on major echo path changes
208-Ball LBGA
MT93L00
M1
N1
P1
N2
R3
Extended
providing
PIN #
architecture
Delay
full-duplex
100 PIN
LQFP
2
3
4
6
8
contains
or
RESET Device Reset (Schmitt Trigger Input). An active low resets the
Name
TRST
64ms
TDO
TCK
Back-to-Back
PIN
TDI
32
Test Serial Data In (3.3V Input). JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
Test Serial Data Out (Output). JTAG serial data is output on
this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG scan is not enabled.
Test Clock (3.3V Input). Provides the clock to the JTAG test
logic.
Test Reset (3.3V Input). Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
MT93L00 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
device and puts the MT93L00 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Control and Status
Registers to their default power-up values.
echo
echo
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Each echo canceller in the MT93L00 has four
functional states: Mute, Bypass, Disable Adaptation
and Enable Adaptation. These are explained in the
section entitled Echo Canceller Functional States.
Adaptive Filter
The adaptive filter adapts to the echo path and
generates an estimate of the echo signal. This echo
estimate is then subtracted from Sin. For each group
of echo cancellers, the adaptive filter is a 1024 tap
FIR adaptive filter which is divided into two sections.
Each section contains 512 taps providing 64ms of
Instability Detector to combat oscillation in very
low ERL environments
Non-Linear Processor for suppression of
residual echo
Disable Tone Detectors for detecting valid
disable tones at send and receive path inputs
Narrow-Band Detector for preventing Adaptive
Filter divergence from narrow-band signals
Offset Null filters for removing the DC
component in PCM channels
12dB attenuator for signal attenuation
Parallel controller interface compatible with
Motorola microcontrollers
PCM encoder/decoder compatible with /A-Law
ITU-T G.711 or Sign-Magnitude coding
Description
Preliminary Information