MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 18

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

18
MT93L00A
Echo Canceller A, Flat Delay Register (FD)
Echo Canceller B, Flat Delay Register (FD)
Echo Canceller A, Decay Step Number Register (NS)
Echo Canceller B, Decay Step Number Register (NS)
Echo Canceller A, Decay Step Size Control Register (SSC)
Echo Canceller B, Decay Step Size Control Register (SSC)
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-
size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo
canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat
delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be
programmed to approximate this expected impulse response thereby improving the convergence characteristics of the Adaptive
Filter. Note that in the following register descriptions, one tap is equivalent to 125 s (64ms/512 taps).
FD
SSC
NS
7-0
7-0
2-0
Amplitude of MU
NS
1.0
FD
7
2
7
Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2
FD
7
of FD
zero.
Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The
decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2
example; If SSC
04h.
Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a
period of SS taps (see SSC
Filter Length (512 or 1024) - [Decay Step Number (NS
For example, if NS
= 256 taps for a filter length of 512 taps.
0
-16
7
7
7-0
Note: Bits marked with “0” are reserved bits and should be written “0”.
7-0
x 8 taps. For example; if FD
Flat Delay (FD
FD
NS
is: 0
6
6
6
0
6
6
FD
2-0
NS
FD
7-0
5
5
7-0
5
= 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC
0
5
5
=4 and SSC
7-0
64 in normal mode and 0
)
FD
2-0
NS
4
4
4
0
4
). The start of the exponential decay is defined as:
4
7-0
2-0
= 5, then MU=2
=4, then the exponential decay start value is 512 - [NS
NS
FD
3
3
3
FIR Filter Length (512 or 1024 taps)
0
3
3
SSC
FD
NS
2
2
2
2
2
2
-16
FD
7-0
for the first 40 taps of the echo canceller FIR filter. The valid range
SSC
FD
NS
1
1
1
7-0
1
128 in extended-delay mode. The default value of FD
1
1
) x Step Size (SS)] where SS = 4 x2
SSC
FD
NS
0
0
0
0
0
0
Read/Write Address: 04h + Base Address
Read/Write Address: 07h + Base Address
Read/Write Address: 06h + Base Address
Read/Write Address: 24h + Base Address
Read/Write Address: 27h + Base Address
Read/Write Address: 26h + Base Address
Step Size (SS)
Preliminary Information
Number of Steps (NS
7-0
-16
x SS] = 512 - [4 x (4x2
). The delay is defined as
SSC2-0
Power Reset Value
Power Reset Value
Power Reset Value
.
SSC2-0
00h
04h
00h
7-0
Time
)
. For
7-0
2-0
4
is
is
)]