MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 12

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

MT93L00A
Memory Mapped Control and Status
registers
Internal memory and registers are memory mapped
into the address space of the HOST interface. The
internal dual ported memory is mapped into
segments on a “per channel” basis to monitor and
control
associated PCM channels. For example, in Normal
configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the
internal address space from 0A0h to 0BFh and
interfaces to PCM channel #5 on all serial PCM I/O
streams.
As illustrated in Figure 7, the “per channel” registers
provide independent control and status bits for each
echo canceller. Figure 8 shows the memory map of
12
Base
Addr +
00h Control Reg A1
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Figure 7 - Memory Mapping of per channel
Control Reg 2
Status Reg
Reserved
Flat Delay Reg
Reserved
Decay Step Size Reg
Decay Step Number
Control Reg A3
Control Reg A4
Noise Scaling
Injection Rate
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Reserved
DTDT Reg
Reserved
NLPTHR
Step Size, MU
Reserved
Reserved
Echo Canceller A
each
Control and Status Registers
individual
Base
Addr +
20h Control Reg B1
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
echo
Control Reg 2
Status Reg
Reserved
Flat Delay Reg
Reserved
Decay Step Size Reg
Decay Step Number
Control Reg B3
Control Reg B4
Noise Scaling
Injection Rate
Rin Peak Detect Reg
Sin Peak Detect Reg
Error Peak Detect Reg
Reserved
DTDT Reg
Reserved
NLPTHR
Step Size, MU
Reserved
Reserved
Echo Canceller B
canceller
and
the control/status register blocks for all echo
cancellers.
When
configuration is selected, Control Register A1/B1 and
Control Register 2 of the selected group of echo
cancellers require special care. Refer to the Register
description section.
Table 2 is a list of the channels used for the 16
groups of echo cancellers when they are configured
as Extended Delay or Back-to-Back
Normal Configuration
For a given group (group 0 to 15), 2 PCM I/O
channels are used. For example, group 1 Echo
Cancellers A and B, channels 2 and 3 are active.
Extended Delay Configuration
For a given group (group 0 to 15), only one PCM I/O
channel is active (Echo Canceller A) and the other
channel carries don’t care data. For example, group
2, Echo Canceller A (Channel 4) will be active and
Echo Canceller B (Channel 5) will carry don’t care
data.
Back-to-Back Configuration
For a given group (group 0 to 15), only one PCM I/O
channel is active (Echo Canceller A) and the other
channel carries don’t care data. For example, group
5, Echo Canceller A (Channel 10) will be active and
Echo Canceller B (Channel 11) will carry don’t care
data.
Group
Table 2 - Group and Channel allocation
0
1
2
3
4
5
6
7
Extended
Channel
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
Preliminary Information
Delay
Group
10
11
12
13
14
15
8
9
or
Back-to-Back
Channel
16, 17
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31