MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 5

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

Preliminary Information
Pin Description (continued)
P16,N16,M16,L16,K16,
T2,T4,T6,T8,T9,T11,
J16,H16,G16,F16,E16,
208-Ball LBGA
T13,T15
B13
B11
D16
M2
A8
B9
B7
B5
A4
G2
H2
K3
K4
PIN #
28,29,30,31,
33,34,35,36,
15,16,17,
19,20,21,
38,39,40
100 PIN
LQFP
22,23
95,97
60
61
62
63
90
92
96
57
58
59
1
PLLVss1
PLLVss2
A0 - A10 Address A0 to A10 (Input). These inputs provide the A10 - A0
D0 - D3,
PLLV
D4 - D7
Name
MCLK
ODE
Rout
TMS
Sout
Fsel
PIN
Rin
C4i
Sin
F0i
DD
Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit
bidirectional data bus of the microprocessor port.
address lines to the internal registers.
Output Drive Enable (Input). This input pin is logically AND’d
with the ODE bit-6 of the Main Control Register. When both ODE
bit and ODE input pin are high, the Rout and Sout ST-BUS
outputs are enabled.
When the ODE bit is low or the ODE input pin is low, the Rout
and Sout ST-BUS outputs are high impedance.
Send PCM Signal Output (Output). Port 1 TDM data output
streams.
Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32
channels per stream.
Receive PCM Signal Output (Output). Port 2 TDM data output
streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s
with 32 channels per stream.
Send PCM Signal Input (Input). Port 2 TDM data input streams.
Sin pin receives serial TDM data streams at 2.048 Mb/s with 32
channels per stream.
Receive PCM Signal Input (Input). Port 1 TDM data input
streams.
Rin pin receives serial TDM data streams at 2.048 Mb/s with 32
channels per stream.
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
Serial Clock (Input). 4.096 MHz serial clock for shifting data in/
out on the serial streams (Rin, Sin, Rout, Sout).
Master Clock (Input). Nominal 10MHz or 20MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 19.2MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 9.6MHz Master Clock input must be applied.
PLL Ground. Must be connected to V
PLL Power Supply. Must be connected to V
Test Mode Select (3.3V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
Description
SS
DD2
MT93L00A
5