MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 10

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

MT93L00A
cancellers. Table 2 shows the 16 groups of 2
cancellers that can be configured into Back-to-Back.
Examples of Back-to-Back configuration include
positioning one group of echo cancellers between a
CODEC and a transmission device or between two
codecs for echo control on analog trunks.
Extended Delay configuration
In this configuration, the two echo cancellers from
the same group are internally cascaded into one 128
milliseconds echo canceller. See Figure 5b. This
configuration uses only one timeslot on PORT1 and
PORT2 and the second timeslot normally associated
with ECB contains undefined data.
Extended Delay configuration is selected by writing
“1” into the ExtDl bit in Echo Canceller A, Control
Register A1. For a given group, only Echo Canceller
A, Control Register A1, has the ExtDl bit. Control
Register B1, bit-0 must always be set to zero.
Table 2 shows the 16 groups of 2 cancellers that can
each be configured into 64ms or 128ms echo tail
capacity.
Echo Canceller Functional States
Each echo canceller has four functional states:
Mute, Bypass, Disable Adaptation and Enable
Adaptation.
10
PORT2
echo
path B
Rout
echo
path A
Sin
a) Normal Configuration (64ms)
channel B
channel A
channel B
channel A
E.C.A
E.C.B
Filter (64ms)
Filter (64ms)
Adaptive
Adaptive
-
-
+
+
Optional -12dB pad
Optional -12dB pad
Figure 5 - Device configuration
PORT1
Sout
Rin
Mute
In Normal and in Extended Delay configurations,
writing a “1” into the MuteR bit replaces Rin with
quiet code which is applied to both the Adaptive
Filter and Rout. Writing a “1” into the MuteS bit
replaces the Sout PCM data with quiet code.
In Back-to-Back configuration, writing a “1” into the
MuteR bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Rout. Writing
a “1” into the MuteS bit of Echo Canceller A, Control
Register 2, causes quiet code to be transmitted on
Sout.
In
configurations, MuteR and MuteS bits of Echo
Canceller B must always be “0”. Refer to Figure 3
and to Control Register 2 for bit description.
Bypass
The Bypass state directly transfers PCM codes from
Rin to Rout and from Sin to Sout. When Bypass
state is selected, the Adaptive Filter coefficients
are reset to zero. Bypass state must be selected for
+Zero
(quiet
code)
PORT2
Rout
echo
path
Sin
Extended
echo
b) Extended Delay Configuration (128ms)
path A
Table 1 - Quiet PCM Code Assignment
PORT2
c) Back-to-Back Configuration (64ms)
Rout
Sin
complement
LINEAR
16 bits
Filter (64ms)
0000h
Adaptive
2’s
E.C.A
-
channel A
channel A
+
E.C.A
Delay
Optional -12dB pad
MAGNITUDE
Preliminary Information
Optional -12dB pad
A-Law
SIGN/
Adaptive Filter
-Law
80h
(128 ms)
and
-
+
Filter (64ms)
Optional -12dB pad
Adaptive
E.C.B
in
+
FFh
-Law
CCITT (G.711)
-
Back -to -Back
PORT1
echo
path
PORT1
A-Law
Sout
Rin
Sout
Rin
D5h