MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 24

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

24
MT93L00A
7-5
Bit
unused
4
3
2
1
0
7
Main Control Register 1
Main Control Register 2
Main Control Register 3
Main Control Register 4
Main Control Register 5
Main Control Register 6
Main Control Register 7
Main Control Register 8
Main Control Register 9
Main Control Register 10
Main Control Register 11
Main Control Register 12
Main Control Register 13
Main Control Register 14
Main Control Register 15
unused
6
unused
Format
MTDBI
MTDAI
PWUP
Name
LAW
unused
5
MTDBI
4
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller B is masked. The Tone Detector operates as specified in Echo
Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from
Echo Canceller A is masked. The Tone Detector operates as specified in Echo
Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select
ITU-T (G.711) PCM code.
When low, both Echo Cancellers A and B for a given group, select sign-magnitude
PCM code
A/ Law: When high, both Echo Cancellers A and B for a given group, select A-Law
companded PCM code.
When low, both Echo Cancellers A and B for a given group, select m-Law companded
PCM code
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given
group, are active.
When low, both Echo Cancellers A and B and Tone Detectors for a given group, are
placed in Power Down mode. In this mode, the corresponding PCM data are bypassed
from Rin to Rout and from Sin to Sout with two frames delay.
When the PWUP bit toggles from zero to one, the echo cancellers A and B execute
their initialization routine which presets their registers, Base Address+00H to Base
Address+3FH, to default Reset Value and clears the Adaptive Filter coefficients.
Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for
their specific application.
MTDAI
3
Format
.
.
2
(EC group 1)
(EC group 2)
(EC group 3)
(EC group 4)
(EC group 5)
(EC group 6)
(EC group 7)
(EC group 8)
(EC group 9)
(EC group 10)
(EC group 11)
(EC group 12)
(EC group 13)
(EC group 14)
(EC group 15)
LAW
1
PWUP
0
Reset Value:
Description
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Read/Write Address:
Preliminary Information
00
H
.
401
402
403
404
405
406
407
408
409
40A
40B
40C
40D
40E
40F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H