MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 13

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

Preliminary Information
Power Up Sequence
On power up, the RESET pin must be held low for
100 s. Forcing the RESET pin low will put the
MT93L00 in power down state. In this state, all
internal clocks are halted, D<7:0>, Sout, Rout, DTA
and IRQ pins are tristated. The 16 Main Control
Registers, the Interrupt FIFO Register and the Test
Register are reset to zero.
When the RESET pin returns to logic high and a
valid MCLK is applied, the user must wait 500 s for
PLL to lock. C4i and F0i can be active during this
period. Once the PLL has locked, the user must
power up the 16 groups of echo cancellers
individually, by writing a “1” into the PWUP bit in
each group of echo canceller’s Main Control
Register.
For each group of echo cancellers, when the PWUP
bit toggles from zero to one, echo cancellers A and B
execute their initialization routine. The initialization
routine sets their registers, Base Address+00
Base Address+3F
clears the Adaptive Filter coefficients. Two frames
are necessary for the initialization routine to execute
properly.
Once the initialization routine is executed, the user
can set the per channel Control Registers, Base
Address+00
application.
Group 0
Echo
Cancellers
Registers
Group 1
Echo
Cancellers
Registers
Groups 2 --> 14
Echo Cancellers
Registers
Group 15
Echo
Cancellers
Registers
Channel 0, EC A Ctrl/Stat Registers
Channel 1, EC B Ctrl/Stat Registers
Channel 2, EC A Ctrl/Stat Registers
Channel 3, EC B Ctrl/Stat Registers
Channel 30, EC A Ctrl/Stat Registers
Channel 31, EC B Ctrl/Stat Registers
Main Control Registers <15:0>
Interrupt FIFO Register
Test Register
Figure 8 - Memory Mapping
H
to Base Address+3F
H
, to the default Reset Value and
H
, for the specific
0000h -->
0020h -->
0040h -->
0060h -->
03C0h -->
03E0h -->
0400h --> 040Fh
0410h
0411h
001Fh
003Fh
005Fh
007Fh
03DFh
03FFh
H
to
Power management
Each group of echo cancellers can be placed in
Power Down mode by writing a “0” into the PWUP bit
in their respective Main Control Register. When a
given
corresponding PCM data are bypassed from Rin to
Rout and from Sin to Sout with two frames delay.
Refer to the Main Control Register section for
description.
The typical power consumption can be calculated
with the following equation:
Call Initialization
To ensure fast initial convergence on a new call, it is
important to clear the Adaptive filter. This is done by
putting the echo canceller in bypass mode for at
least one frame (125
adaptation.
Interrupts
The MT93L00 provides an interrupt pin (IRQ) to
indicate to the HOST processor when a G.164 or
G.165 Tone Disable is detected and released.
Although the MT93L00 may be configured to react
automatically to tone disable status on any input
PCM voice channels, the user may want for the
external HOST processor to respond to Tone
Disable information in an appropriate, application
specific manner.
Each echo canceller will generate an interrupt when
a Tone Disable occurs and will generate another
interrupt when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read
the Interrupt FIFO Register. This register is a FIFO
memory containing the channel number of the echo
canceller that has generated the interrupt.
All pending interrupts from any of the echo
cancellers and their associated input channel
number are stored in this FIFO memory. The IRQ
always returns high after a read access to the
Interrupt FIFO Register. The IRQ pin will toggle low
for each pending interrupt.
where 0
group
P
C
= 9 * Nb_of_groups + 3.6, in mW
Nb_of_groups
is
in
Power
s) and then enabling
16
Down
MT93L00A
mode,
the
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