MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 19

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

Preliminary Information
Echo Canceller A, Noise Scaling (NS)
Echo Canceller B, Noise Scaling (NS)
If the comfort noise level estimator is unable to correctly match the background noise level, this register can be used to scale the
comfort noise up or down. A neutral value of 80h will prevent any scaling. Values less than 80h will scale the comfort noise level
down. Values greater than 80h will scale the comfort noise level up. Scaling is done linearly, so to scale the comfort noise down by 1
dB, a value of 72h would be used (-1 dB = 89% of original level, 0.89
8Fh (1 dB = 112% of original level, 1.12
7-4
6-4
3-0
Bit
Bit
3
2
1
0
7
res
0
7
7
Echo Canceller A, Control Register A3
Echo Canceller B, Control Register B3
Echo Canceller A, Control Register A4
Echo Canceller B, Control Register B4
NS
7
7
SD
res
6
6
2
PathDet
SupDec
RingClr
PathClr
Name
Name
NS
res
res
res
6
SD
0
res
6
5
5
1
NS
SD
res
4
4
5
0
5
Reserved bits. Must always be set to zero for normal operation.
When high, the instability detector is activated. When low, the instability detector is
disabled
When high, the current echo channel estimate will be cleared and the echo canceller
will enter fast convergence mode upon detection of a path change. When low, the
echo canceller will keep the current path estimate but revert to fast convergence
mode upon detection of a path change. Note: this bit is ignored if PathDet is low.
When high, the path change detector is activated. When low, the path change
detector is disabled.
Reserved bit. Must always be set to zero for normal operation.
Must be set to zero.
These three bits control how long the echo canceller remains in a fast convergence
state following a path change, Reset or Bypass operation. A value of zero will keep
the echo canceller in fast convergence indefinitely.
Reserved bits. Must always be set to zero for normal operation.
RingClr
res
3
3
NS
4
4
PathClr
(dec)
res
2
2
NS
• 80h = 8Fh).
3
PathDet
3
res
1
1
NS
2
2
res
res
0
0
NS
1
1
(dec)
Read/Write Address: 08
Read/Write Address: 28
Reset Value:
Read/Write Address: 09
Read/Write Address: 29
Reset Value:
Description
Description
• 80h = 72h). Similarly, to scale up by 1 dB, use a value of
NS
0
Read/Write Address: 0Ah + Base Address
Read/Write Address: 2Ah + Base Address
0
0A
50
H
H
H
H
H
H
.
+ Base Address
+ Base Address
+ Base Address
+ Base Address
.
Power Reset Value
74h
MT93L00A
19