MT93L00AB Zarlink Semiconductor, MT93L00AB Datasheet - Page 16

• Manufacturer Part Number: MT93L00AB
• Description: Description = Multi-channel Voice Echo CANceller ;; Package Type = LQFP ;; No. Of Pins = 100
• Manufacturer: Zarlink Semiconductor

16
MT93L00A
Bit
Bit
TDis
7
6
5
4
3
2
1
0
7
6
5
4
3
2
res
7
7
Echo Canceller A, Control Register A2
Echo Canceller B, Control Register B2
Echo Canceller A, Status Register
Echo Canceller B, Status Register
PHDis
TD
6
6
NLPDis
AutoTD
HPFDis
MuteS
MuteR
DTDet
PHDis
NBDis
Name
Name
TDis
NLPDis
DTDet
res
TD
res
res
res
5
5
AutoTD
res
4
4
When high, tone detection is disabled. When low, tone detection is enabled.
When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are
disabled entirely and are put into power down mode.
When high, the tone detectors will trigger upon the presence of a 2100Hz tone
regardless of the presence/absence of periodic phase reversals.
When low, the tone detectors will trigger only upon the presence of a 2100Hz tone
with periodic phase reversals.
When high, the non-linear processor is disabled.
When low, the non-linear processors function normally. Useful for G.165 conformance
testing.
When high, the echo canceller puts itself in Bypass mode when the tone detectors
detect the presence of 2100Hz tone. See PHDis for qualification of 2100Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state
of the 2100Hz tone detectors.
When high, the narrow-band detector is disabled. When low, the narrow-band
detector is enabled.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When low, the offset nulling filters are active and will remove DC offsets on PCM input
signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
Reserved bit.
Logic high indicates the presence of a 2100Hz tone.
Logic high indicates the presence of a double-talk condition.
Reserved bit.
Reserved bit.
Reserved bit.
NBDis
res
3
3
HPFDis
res
2
2
MuteS
TDG
1
1
MuteR
NB
0
0
Read/Write Address: 01
Read/Write Address: 21
Reset Value:
Read Address:
Read Address:
Reset Value:
Description
Description
Preliminary Information
00
02
22
00
H
H
H
H
H
H
.
.
+ Base Address
+ Base Address
+ Base Address
+ Base Address