MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 28

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 22: Identification Register Definitions
Table 23: Scan Register Sizes
Table 24: Instruction Codes
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
INSTRUCTION FIELD
REGISTER NAME
INSTRUCTION
Revision Number
(31:28)
Device Depth
(27:23)
Device Width
(22:18)
Micron Device ID
(17:12)
Micron JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
Instruction
Bypass
ID
Boundary Scan: x18, x32, x36
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
CODE
000
001
010
011
100
101
110
111
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
CONFIGURATION DESCRIPTION
00000101100
xxxxxx
BIT SIZE
00111
00110
00011
00100
0000
BIT
1
32
75
3
1
Reserved for version number.
Defines depth of 1Mb.
Defines depth of 512K.
Defines width of x18 bits.
Defines width of x32 or x36 bits.
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
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PIPELINED, SCD SYNCBURST SRAM
18Mb: 1 MEG x 18, 512K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.