MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 18

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE:
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. Timing diagram is shown assuming that the device was not enabled before entering into this sequence. OE# does not
4. Outputs are disabled within one clock cycle after deselect.
GW#, BWE#,
BWa#-BWd#
is HIGH, CE2# is HIGH and CE2 is LOW.
cause Q to be driven until after the following clock rising edge. (This note applies to whole diagram.)
ADDRESS
(NOTE 2)
ADSP#
ADSC#
ADV#
OE#
CLK
CE#
Q
t ADSS
t AS
t CES
A1
t ADSH
t AH
t CEH
t KH
(NOTE 3)
High-Z
t KC
t WS
t KL
Single READ
t KQLZ
t WH
t KQ
t ADSS
A2
Q(A1)
t ADSH
t OEHZ
t AAS
t AAH
t OELZ
t OEQ
READ Timing
(NOTE 1)
Q(A2)
Figure 7:
t KQX
t KQ
18
Q(A2 + 1)
PIPELINED, SCD SYNCBURST SRAM
18Mb: 1 MEG x 18, 512K x 32/36
ADV#
suspends
burst.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q(A2 + 2)
BURST READ
Q(A2 + 3)
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
DON’T CARE
Q(A2 + 1)
©2003 Micron Technology, Inc.
t KQHZ
Deselect
cycle
UNDEFINED
(NOTE 4)