MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 17

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

Notes
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
10. Typical values are measured at 2.5V, 25
11. Test conditions as specified with the output load-
3. For 2.5V V
4. The MODE and ZZ pins/balls have an internal
5. V
6. This parameter is sampled.
7. I
8. “Device deselected” means device is in power-
9. Typical values are measured at 3.3V, 25
1. All voltages referenced to V
2. For 3.3V V
Overshoot:
Undershoot: V
Power-up:
Overshoot: V
Undershoot: V
Power-up:
pull-up/pull-down and input leakage = ±10µA.
can be connected together.
increases with faster cycle times. I
with faster cycle times and greater output loading.
down mode as defined in the truth table. “Device
selected” means device is active (not in power-
down mode).
10ns cycle time.
10ns cycle time.
ing shown in Figures 11 and 12 for 3.3V I/O and
DD
DD
200ms
200ms
Q should never exceed V
is specified with no output current and
DD
DD
:
:
V
V
V
IH
IH
IL
IH
IH
IL
³ -0.5V for t £
£ +2.65V and V
£ +3.6V for t £
³ -0.7V for t £
£ +3.6V and V
£ +4.6V for t £
SS
(GND).
DD
t
t
KC/2 for I £ 20mA
t
t
DD
KC/2 for I £ 20mA
KC/2 for I £ 20mA
DD
KC/2 for I £ 20mA
. V
£ 3.135V for t £
£ 2.375V for t £
DD
DD
Q increases
and V
º
º
C, and
C, and
DD
Q
17
PIPELINED, SCD SYNCBURST SRAM
12. Measured as HIGH above V
13. This parameter is measured with the output load-
14. Refer to Technical Note TN-58-09, “Synchronous
15. OE# is a “Don’t Care” when a byte write enable is
16. A WRITE cycle is defined by at least one byte write
17. This is a synchronous device. All addresses must
18Mb: 1 MEG x 18, 512K x 32/36
Figures 13 and 14 for 2.5V I/O unless otherwise
noted.
ing shown in Figure 12 for 3.3V I/O and Figure 14
for 2.5V I/O.
SRAM Bus Contention Design Considerations,”
for a more thorough discussion of these parame-
ters.
sampled LOW.
(BWa#–BWd#) being LOW, the byte write enable
(BWE#) active, and ADSC# LOW for the required
setup and hold times. A READ cycle is defined by
the byte write enable (BWE#) being HIGH or
ADSP# LOW for the required setup and hold
times.
meet the specified setup and hold times when
either ADSC# or ADSP# is LOW and chip is
enabled. All other synchronous inputs must meet
the setup and hold times with stable logic levels
for all rising edges of CLK when the chip is
enabled. To remain enabled, chip enable must be
valid at each rising edge when either ADSC# or
ADSP# is LOW.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
and LOW below V
©2003 Micron Technology, Inc.
IL
.