MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 20

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE:
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. This undefined READ will follow any WRITE cycle which is transitioned to a Read, Deselect, or Snooze.
BWa#-BWd#
is HIGH, CE2# is HIGH and CE2 is LOW.
ADDRESS
(NOTE 4)
(NOTE 2)
(NOTE 3)
ADSC#
ADSP#
BWE#,
ADV#
OE#
CLK
CE#
Q
D
A1
High-Z
High-Z
t ADSS
t CES
t AS
A2
Back-to-Back READs
t ADSH
t CEH
t KH
t AH
t KC
t KQLZ
(NOTE 5)
Q(A1)
t KL
t KQ
Q(A2)
t OEHZ
t WS
Single WRITE
t DS
D(A3)
READ/WRITE Timing
A3
t DH
t WH
Figure 9:
A4
20
t OELZ
PIPELINED, SCD SYNCBURST SRAM
(NOTE 6)
18Mb: 1 MEG x 18, 512K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(NOTE 1)
Q(A4)
BURST READ
Q(A4+1)
Q(A4+2)
Q(A4+3)
DON’T CARE
©2003 Micron Technology, Inc.
D(A5)
A5
Back-to-Back
WRITEs
UNDEFINED
D(A6)
A6