MT57W1MH18B Micron Semiconductor Products, Inc., MT57W1MH18B Datasheet - Page 3

• Manufacturer Part Number: MT57W1MH18B
• Description: 18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Programmable Impedance Output
Buffer
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
resistor must be five times the desired impedance. For
example, a 350 W resistor is required for an output
impedance of 70 W . To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175 W to 350 W . Alternately, the ZQ ball
can be connected directly to V
the device in a minimum impedance mode.
because, over time, variations may occur in supply
voltage and temperature. The device samples the value
of RQ. Impedance updates are transparent to the sys-
tem; they do not affect device operation, and all data
sheet timing and current specifications are met during
an update.
set at 50 W . To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
18Mb: 1.8V V
MT57W1MH18B_H.fm – Rev. H, Pub. 3/03
The DDR SRAM is equipped with programmable
Output impedance updates may be required
The device will power up with an output impedance
DD
, HSTL, DDRIIb2 SRAM
DD
Q, which will place
SS
. The value of the
3
2 MEG
Clock Considerations
maximum output, data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry
automatically resets the DLL when the absence of
input clock is detected. See Micron Technical Note TN-
54-02 for more information on clock DLL start-up pro-
cedures.
Single Clock Mode
pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
Depth Expansion
trol signal for each bank. All other control signals can
be common between banks as appropriate.
This device utilizes internal delay-locked loops for
The SRAM can be used with the single K, K# clock
The output echo clocks are precise references to
Depth expansion requires replicating the LD# con-
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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8, 1 MEG
DD
, HSTL, DDRIIb2 SRAM
X
18, 512K
©2003 Micron Technology, Inc.
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