MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 8

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
The MAXQ3108 microcontroller is an integrated, low-
cost solution to simplify the design of electricity meter-
ing and industrial control products. Standard features
include two highly optimized, single-cycle, MAXQ 16-bit
RISC microcontroller cores; 64KB of flash memory,
11KB RAM, and independent hardware stacks; gener-
al-purpose registers; and data pointers for each core.
Application-specific peripherals include hardware SPI
and I
generators, dual UARTs (one of which that supports IR
carrier frequency modulation), and math accelerators.
At the heart of the MAXQ3108 are two MAXQ20 16-bit
RISC microcontrollers. The dual-core approach allows
one core (DSPCore) to be entirely dedicated to collec-
tion and processing of AFE samples for the metering
function, while the second core handles any communi-
cation and user-specific administrative functions. The
MAXQ3108 DSPCore operates at 10.027MHz with the
default crystal and almost all instructions execute in a
single clock cycle (100ns), while the UserCore runs at
half that frequency (5.014MHz).
The dual-core strategy promotes flexibility by allowing
the update of metering routines and parameters sepa-
rately in DSPCore code and data memory. Furthermore,
an independent DSPCore solely responsible for accu-
rate metering introduces a measure of safety and relia-
bility since all administrative/communication functions
and interruptions are handled by the UserCore. Both
cores feature standard MAXQ power-saving system
8
1, 28, 27, 26,
25, 8, 9
_______________________________________________________________________________________
PIN
2
C masters, real-time clock, programmable pulse
P2.0–P2.6
NAME
Detailed Description
Port 2. Port 2 functions as both a 7-bit I/O port and as a special function interface to the CF pulse
generator outputs, clock output, and the Manchester ENDEC or SPI. The default reset condition of
the pins is weakly pulled up (input), with exception of P2.5 and P2.6, which are always outputs
and default to strong high. To drive output, either the port direction register must be programmed
to enable output, or the alternate function module must be configured to drive the pins. P2.5 and
P2.6 are accessible to the DSPCore only.
PIN
28
27
26
25
1
8
9
PORT
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
clock-divide modes and independently implement low-
power stop (UserCore) and idle (DSPCore) modes. The
DSPCore implements an idle mode that allows CPU
execution to be halted while awaiting an ADC sample.
The UserCore implements an ultra-low-power stop
mode that automatically disables the DSPCore and
results in a quiescent current consumption of less than
1.5μA. The combination of high performance and core-
specific low-power mode implementation provides
increased power efficiency and capability over compet-
itive microcontrollers.
The MAXQ20 is a low-power implementation of the new
16-bit MAXQ family of RISC cores. The core supports
the Harvard memory architecture with separate 16-bit
program and data address buses, but also provides
pseudo-Von Neumann support through utility ROM
functions. A fixed 16-bit instruction is standard, but
data can be arranged in 8 or 16 bits. The MAXQ20 core
is implemented as a nonpipelined processor with single
clock-cycle instruction execution. The data path is
implemented around register modules, and each regis-
ter module contributes specific functions to the core.
The accumulator module consists of sixteen 16-bit reg-
isters and is tightly coupled to the arithmetic logic unit
(ALU). Program flow is supported by a dedicated 16-
level-deep hardware stack.
Execution of instructions is triggered by data transfer
between functional register modules, or between a
functional register module and memory. Since data
FUNCTION
Pin Description (continued)
ALTERNATE FUNCTION
MDIN2N/MISO
MDIN2P/MOSI
MDIN0N/SSEL
SCLK/CLKO
MDIN0P
Microprocessor
CF1
CF2