MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 23

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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PI0 (02h, 01h)
Initialization:
Read/Write Access:
PI0.[7:0]:
PI1 (03h, 01h)
Initialization:
Read/Write Access:
PI1.[6:0]:
PI1.7: Reserved
EIF0 (04h, 01h)
Initialization:
Read/Write Access:
EIF0.[7:0]: IE[7:0]
EIE0 (05h, 01h)
Initialization:
Read/Write Access:
EIE0.[7:0]: EX[7:0]
EIF1 (06h, 01h)
Initialization:
Read/Write Access:
EIF1.[3:0]: IE[11:8]
EIF1.[7:4]: Reserved
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Low-Power, Dual-Core Microcontroller
Port 0 Input Register
The reset value for this register is dependent on the logical states of the pins.
Unrestricted read-only.
Port 0 Input Register Bits 7:0. The PI0 register always reflects the logic state of its pins when read.
Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel
pullup transistor is controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is
on, if the PO bit is cleared to 0, the weak pullup is off and forces the port pin into three-state.
Port 1 Input Register
The reset value for this register is 0sssssssb, where “s” depends on the logical state of the pin.
Unrestricted read.
Port 1 Input Register Bits 6:0. The PI1 register always reflects the logic state of its pins when read.
Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel
pullup transistor is controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is
on, if the PO bit is cleared to 0, the weak pullup is off and forces the port pin into three-state.
Reserved. Read returns 0.
External Interrupt Flag 0 Register
EIF0 is cleared to 00h on all forms of reset.
Unrestricted read/write.
Interrupt Edge Detect Bits 7:0. These bits are set when a negative edge (ITx = 1) or a positive
edge (ITx = 0) is detected on the interrupt x pin. Setting any of the bits to 1 generates an interrupt to
the CPU if the corresponding interrupt is enabled. This bit remains set until cleared by software or a
reset. It must be cleared by software before exiting the interrupt source routine or another interrupt
is generated as long as the bit remains set.
External Interrupt Enable 0 Register
EIE0 is cleared to 00h on all forms of reset.
Unrestricted read/write.
Enable External Interrupt Bits 7:0. Setting any of these bits to 1 enables the corresponding
external interrupt. Clearing any of the bits to 0 disables the corresponding interrupt function.
External Interrupt Flag 1 Register
EIF1 is cleared to 00h on all forms of reset.
Unrestricted read/write.
Interrupt Edge Detect Bits 11:8. These bits are set when a negative edge (ITx = 1) or a positive
edge (ITx = 0) is detected on the interrupt x pin. Setting any of the bits to 1 generates an interrupt to
the CPU if the corresponding interrupt is enabled. This bit remains set until cleared by software or a
reset. It must be cleared by software before exiting the interrupt source routine or another interrupt
is generated as long as the bit remains set.
Reserved. Reads return 0.
Special Function Register Bit Descriptions (continued)
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