MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 42

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

www.DataSheet4U.com
Low-Power, Dual-Core Microcontroller
42
SPICF (0Eh, 03h)
Initialization:
Read/Write Access:
SPICF.0: CKPOL
SPICF.1: CKPHA
SPICF.2: CHR
SPICF.[6:3]: Reserved
SPICF.7: ESPII
SPICK (0Fh, 03h)
Initialization:
Read/Write Access:
SPICK.[7:0]:
I2CBUF (00h, 04h)
Initialization:
Read/Write Access:
I2CBUF.[9:0]:
I2CBUF.[15:10]: Reserved
I2CST (01h, 04h)
Initialization:
Read/Write Access:
I2CST.0: I2CSRI
______________________________________________________________________________________
SPI Configuration Register
This buffer is cleared to 00h on all forms of reset.
Unrestricted read/write.
Clock Polarity Select. This bit is used with the CKPHA bit to determine the SPI transfer format.
When the CKPOL is set to 1, the SPI uses the clock falling edge as an active edge. When the
CKPOL is cleared to 0, the SPI selects the clock rising edge as an active edge.
Clock Phase Select. This bit is used with the CKPOL bit to determine the SPI transfer format. When
the CKPHA is set to 1, the SPI samples input data at an inactive edge. When the CKPHA is cleared
to 0, the SPI samples input data at an active edge.
Character Length Bit. The CHR bit determines the character length for an SPI transfer cycle. A
character can consist of 8 or 16 bits in length. When CHR bit is 0, the character is 8 bits; when
CHR is set to 1, the character is 16 bits.
Reserved. Reads return 0.
SPI Interrupt Enable. Setting this bit to 1 enables the SPI interrupt when the MODF, WCOL, ROVR,
or SPIC flags are set. Clearing this bit to 0 disables the SPI interrupt.
SPI Clock Register
This buffer is cleared to 00h on all forms of reset.
Unrestricted read/write.
Clock Divide Ratio Bit 7:0. These bits select one of the 256 divide ratios (0 to 255) used for the
baud-rate generator, with bit 7 as the most significant bit. The frequency of the SPI baud rate is
calculated using the following equation:
This register has no function when operating in slave mode, and the clock generation circuitry
should be disabled.
I
This register is cleared to 0000h on all forms of resets.
Unrestricted read access. This register can be written to only when I2CBUSY = 0.
I2C Data Buffer Bits 9:0. Data for I
transmit and receive buffers are separate but both are addressed at this location. During address
transmission, I2CBUF[6:0] is used as the address bits. During data transmission, only I2CBUF[7:0]
is used.
Reserved. Reads return 0.
I
This register is cleared to 0000h on all forms of reset.
Unrestricted read. Not all the bits can be written by software. For each bit accessibility, see the
individual bit description.
I
must be cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if
enabled.
2
2
2
C Data Buffer Register (16-Bit Register)
C Status Register (16-Bit Register)
C START Interrupt Flag. This bit is set to 1 when a START condition (S or Sr) is detected. This bit
Special Function Register Bit Descriptions (continued)
SPI Baud Rate = 0.5 x System Clock/(Divide Ratio + 1)
2
C transfer is read from or written to this location. The I
2
C