MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 46

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
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SMD1 (08h, 04h)
Initialization:
Read/Write Access:
SMD1.0: FEDE
SMD1.1: SMOD
SMD1.2: ESI
SMD1.[7:3]: Reserved
PR1 (09h, 04h)
Initialization:
Read/Write Access:
PR1.[15:0]:
TB0CN (0Ah, 04h)
Initialization:
Read/Write Access:
TB0CN.0: CP/ RLB
TB0CN.1: ETB
TB0CN.2: TRB
TB0CN.3: EXENB
TB0CN.4: DCEN
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Serial Port Mode Register 1
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Framing-Error-Detection Enable. This bit selects the function of SM0 (SCON1.7).
Serial Port 0 Baud-Rate Select. The SMOD selects the final baud rate for the asynchronous mode.
Enable Serial Port 0 Interrupt. Setting this bit to 1 enables interrupt requests generated by the RI
or TI flags in SCON1. Clearing this bit to 0 disables the serial-port interrupt.
Reserved. Reads return 0.
Phase Register 1
The phase register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Phase Register 1 15:0. This register is used to load and read the 16-bit value in the phase register
that determines the baud rate for the serial port 1.
Timer B 0 Control
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Capture/Reload Select. This bit determines whether the capture or reload function is used for timer
B. Timer B functions in an autoreload mode following each overflow/underflow. See the TFB bit
description for overflow/underflow condition. Setting this bit to 1 causes a timer B capture to occur
when a falling edge is detected on TBB if EXENB is 1. Clearing this bit to 0 causes an autoreload
to occur when timer B overflow or a falling edge is detected on TBB if EXENB is 1. It is not intended
that the timer B compare functionality should be used when operating in capture mode.
Enable Timer B Interrupt. Setting this bit to 1 enables the interrupt from the timer B TFB and EXFB
flags in TBCN. In timer B clock output mode (TBOE = 1), the timer overflow flag (TFB) is still set on
an overflow; however, the TBOE = 1 condition prevents this flag from causing an interrupt when
ETB = 1.
Timer B Run Control. This bit enables timer B operation when set to 1. Clearing this bit to 0 halts
timer B operation and preserves the current count in TBV.
Timer B External Enable. Setting this bit to 1 enables the capture/reload function on the TBB pin
for a negative transition (in upcounting mode). A reload results in TBV being reset to 0000h.
Clearing this bit to 0 causes timer B to ignore all external events on TBB pin. When operating in
autoreload mode (CP/RLB = 0) with the PWM output functionality enabled, enabling the TBB input
function (EXENB = 1) allows the PWM output negative transitions to set the EXFB flag. However, no
reload occurs as a result of the external negative-edge detection.
Down-Count Enable. This bit, in conjunction with the TBB pin, controls the direction that timer B
counts in 16-bit autoreload mode. Clearing this bit to 0 causes timer B to count up only. Setting
this bit to 1 enables the up/down counting mode (i.e., it causes timer B to count up if the TBB pin
is 1 and to count down if the TBB pin is 0). When timer B PWM output mode functionality is
enabled along with up/down counting (DCEN = 1), the up/down count control of timer B is
controlled internally based upon the count in relation to the register settings. In the compare
modes, the DCEN bit controls whether the timer counts up and resets (DCEN = 0), or counts up and
down (DCEN = 1).
FEDE = 0: SCON1.7 functions as SM0 for serial-port mode selection.
FEDE = 1: SCON1.7 is converted to the FE flag.
SMOD = 1: 16 times the baud clock for mode 1 and 3; 32 times the system clock for mode 2.
SMOD = 0: 64 times the baud clock for mode 1 and 3; 64 times the system clock for mode 2.
Special Function Register Bit Descriptions (continued)