MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 26

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
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FCNTL (0Dh, 01h)
Initialization:
Read/Write Access:
FCNTL.[2:0]: FC[2:0]
FCNTL.[6:3]: Reserved
FCNTL.7: FBUSY
FDATA (0Eh, 01h)
Initialization:
Read/Write Access:
FDATA.[15:0]:
PWCN (0Fh, 01h)
Initialization:
Read/Write Access:
PWCN.0: FLLEN
PWCN.1: FLOCK
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Flash Memory Control Register
This register is set to 80h on POR and is unaffected by all other forms of reset.
Unrestricted read, bits 2:0 are write accessible only by utility ROM or logical data memory. (This
register is not accessible by program code inside the flash memory because of the rule governing
the pseudo-Von Neumann mapping. Access is blocked by hardware.) Also, write access to FCNTL
is prohibited when FBUSY is 0.
Flash Command Bits 2:0. The below table shows the commands for flash operations provided by
these bits. The MMU supports only these commands; other settings are reserved. Using any
reserved command results in no operation.
Reserved. Reads return 0.
Flash Busy. This busy flag is cleared to a logic 0 to indicate the start of an erase/program
operation by the MMU immediately following the command sequence. It is hold low until the end of
the operation. Set/reset of this flag is synchronized with the system clock.
Flash Memory Data Register
This register is cleared to 0000h on all forms of reset.
Unrestricted read, write accessible only by utility ROM or logical data memory. (This register is not
accessible for program code inside the flash memory due to the rule governing the pseudo-Von
Neumann mapping.). Also, write access to FCNTL is prohibited when FBUSY is 0.
This register is used by the user software or the ROM loader to support the flash
erase/program/verify operation. Writing to this SFR has no effect on flash operation until a valid
flash command is first entered through the FC[2:0] bits of the FCNTL SFR. All flash operation must
be initiated by providing a valid command in the FCNTL control register followed by writing target
address and data by the FDATA SFR (when required by the command).
Power Control Register (16-Bit Register)
Implemented register bits (except for the ECLKO and ENDSP bit) are unaffected by resets other than
power-on reset. The ECLKO and ENDSP bits are reset to 0 on any reset. On power-on reset, this
register is reset to 0000h (except that HFXD is 1 for PCK = 11b).
Unrestricted read. FLOCK and 32KRDY are read-only.
FLL Lock Enable. Setting this bit to 1 enables the FLL if it is not already running, and causes it to
lock to the 32K input. When this bit is cleared to 0, the FLL is disabled if it is not providing the
system clock.
FLL Locked. This is a read-only status bit. This bit is automatically reset to 0 when FLLEN is
changed from 0 to 1 and set to 1 when the FLL is locked to the 32.768kHz clock. This bit is also
reset to 0 on entry to stop mode.
Special Function Register Bit Descriptions (continued)
FC[2:0]
000
001
010
011
100
101
110
111
Read Mode (default)
Verify Information Block
Write Information Block
Write Main Memory Block
Erase Information Block
Page Erase of Main Memory Block
Mass Erase of Main Memory Block
Load Trim Information
FLASH COMMANDS