MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 58

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
3) Load the command byte into I2CBUF. The com-
4) Monitor the I2CTXI flag in the I2CST register. When
5) Set the I2CACK bit to 0 to acknowledge the first
6) Monitor the I2CRXI flag in the I2CST register. When
7) Clear the I2CACK bit to NAK the next received byte.
8) Monitor the I2CRXI flag in the I2CST register. When
9) Set the I2CSTOP bit in the I2CCN register. This
I
Bytes from External Master
1) Set the I2CEN bit in the I2CCN register. This
Figure 3. ADC Bit Stream Decoder
58
2
C Use Scenario: MAXQ3108 Slave Receives 2
sent (and both SDA and SCL are low), the
I2CSTART bit is cleared. Note that the I2CSRI bit is
set in the I2CST register as well. That is because
the I
mand byte consists of the slave address and the
R/W bit. For this example, assume we wish to write
to slave address 0x30. The byte to be loaded in this
case is 0x60: the address shifted up by one posi-
tion and bit 0 (the R/W bit) set to a one.
set, the I
command byte and has received an ACK or a NAK
from the remote device. Check the I2CNACKI flag
in the I2CST register to determine if an ACK or a
NAK was received. If set, the command was not
acknowledged. Clear these bits after they are test-
ed.
byte.
set, the I
data byte and has sent the ACK. Read the data
from the I2CBUF register and clear the I2CRXI bit.
set, the I
data byte and has sent the NAK. Read the data
from the I2CBUF register and clear the I2CRXI bit.
causes the MAXQ3108 to send the STOP
sequence. When this bit returns to 0, the STOP
sequence has been sent and the I
enables the I
______________________________________________________________________________________
2
C peripheral sees its own START condition.
2
2
2
C peripheral has finished receiving the
C peripheral has finished receiving the
C peripheral has finished sending the
2
C peripheral.
MDINxN
MDINxP
2
C bus is idle.
MANCHESTER
DECODER
CLOCK
DATA
2) Set the slave address in the I2CSLA register.
3) Monitor I2CST. As conditions change on the I
4) Set the I2CACK bit to 0 to ACK the received bytes.
5) Monitor the I2CRXI and the I2CSPI flags in the
6) When the I2CSPI flag is set, the I
The MAXQ3108 contains six cubic sinc filters that
receive decoded bit streams from three Manchester
decoders. The ADC hardware is unique in that most of
the functions can be performed by either the UserCore
or the DSPCore. This section describes how these ADC
inputs are configured. See Figure 3.
The input to the Manchester decoder is a composite
signal consisting of two delta-sigma modulator chan-
nels and a synchronization signal. The decoder
extracts the clock and data and presents the signals to
a sync detector. This block searches for the synchro-
nization pattern and keeps a shift register in step with
the synchronized signal. When the sync detector is
asserting a lock indication, the recovered channel 0
and 1 outputs reflect two analog inputs at the ADC
modulator.
These recovered bit streams are presented to cubic
sinc filters for conversion to digital format. The filters
themselves have 24-bit resolution; however, the number
of bits that are actually significant depends directly on
the oversampling rate used in the filter control logic.
bus, they are reflected in the I2CST register. When
the I2CAMI bit is set, the address of the MAXQ3108
has been matched. The MAXQ3108 automatically
sends ACK when an address matches.
I2CST register. When the I2CRXI bit is set, the I
peripheral has finished receiving the data byte and
has sent the ACK. Read the data from the I2CBUF
register and clear the I2CRXI bit.
detected a STOP condition. No more characters are
to be expected.
DETECTOR
SYNC
ΔΣ CH0
ΔΣ CH1
LOCK
2
C peripheral has
ADC Inputs
2
2
C
C