MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 52

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

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Low-Power, Dual-Core Microcontroller
• Internal FLL, optionally driven by the 32,768Hz exter-
The 32,768Hz external crystal provides the clock refer-
ence for functional units that require a fixed frequency.
When the 32,768Hz clock reference is used directly as
the system clock, the MAXQ3108 is operating in power-
saving mode.
When not operating in power-saving mode, the
MAXQ3108 receives its clock from the FLL. Because
the MAXQ3108 has no way to receive a high-frequency
clock from an external crystal or other source, the FLL
is the only source of a high-frequency clock.
The FLL must be selected as the clock source for
normal operation. This selection is made through the
FLLSL bit. The FLLSL bit controls selection of the inter-
nal FLL oscillator for system clock generation. When
FLLSL = 1, the internal FLL oscillator is used for system
clock generation. The FLLSL bit is read/write accessi-
ble at any time and defaults to logic 0 on power-on
reset only. One of the first tasks user software
should perform is to set the FLLSL bit to 1.
During a power-on reset, the 32,768Hz crystal amplifier
is automatically enabled. To disable the internal crystal
amplifier, the PWCN.X32D bit must be set to 1. Once
the 32,768Hz crystal amplifier is enabled, 250ms is
required for it to warm up. The PWCN.32KRDY bit is set
to 1 once the 32,768Hz amplifier has been given suffi-
cient time to warm up.
The external 32K clock source can operate in different
modes according to the setting of the 32K mode bits
(PWCN.32KMD). In normal operation, the 32K oscillator
is operating in the noise immune mode (32KMD = 00),
which is more tolerant to system noise. If the system is
operating in a very quiet environment, the oscillator can
be switched to quiet mode (32KMD = 01) with reduced
current consumption. Note that in this mode, the oscilla-
tor is subject to system noise and may not be desirable
for very accurate timing requirement.
For applications where low stop-mode current is
desired, there is an option to invoke the quiet mode
operation during stop mode. When 32KMD = 1x, the
quiet mode is invoked on entry to stop mode. If 32KMD
= 10 and 32K is enabled (X32D = 0), the CPU is held in
stop mode until the 32K oscillator has warmed up
(32KRDY = 1). If 32KMD = 11, the CPU starts execution
from the selected clock source after the required FLL
cycles requirement, in parallel with the oscillator
warmup (transition from quiet mode to noise immune
mode).
52
nal crystal or resonator
______________________________________________________________________________________
32,768Hz Crystal Oscillator
When the 32K input is enabled (X32D = 0), changes of
the 32KMD bits reset the 32KRDY bit if the 32K circuitry
is already opening in the quiet mode and the new set-
ting requires to change to noise immune mode. When
the oscillator is operating in quiet mode, no warmup
time is required and, therefore, 32KRDY is always set to
1. If the operation mode is changed to noise immune
mode from the quiet mode, the 32KRDY bit is reset to 0.
The 32KRDY bit is set to 1 after the necessary warmup
time requirement.
The internal FLL offers the least expensive solution for
clock generation. The FLL provides a maximum fre-
quency of 306 times the CX1 input clock (32.768kHz x
306 = 10.027MHz) with ±5% when locked with
32.768kHz quartz crystal source. The lock period for
the FLL is about 64 cycles of the CX1 input clock
(approximately 2ms).
Controlling the FLL: The FLL has a lock-enable bit
(FLLEN) to initiate the locking mechanism to the 32K
input source. The FLOCK bit indicates to the user that
the FLL is locked and ready to be used. The FLL has a
short warmup period where the FLL is running but is not
locked. The FLOCK bit indicates that the FLL is running
and locked to the CX1 input. The FLL oscillator clock is
divided down according to the PMME.
Internal clocks are generated directly from the system
clock. Normally, the system clock is sourced from one
of the two clock sources. The effect of the PMME and
CD bits on the system clock in the MAXQ3108 is sum-
marized in Table 6.
When the 32,768Hz clock is selected as the system
clock source (PMME, CD1, CD0 = 111b), the system is
running at PMM2 mode and all functional units are run-
ning synchronously. In this mode of operation, the high-
frequency clock source is turned off to save power if
the switchback function is not enabled (SWB = 0)
unless the DSPCore is enabled; if the switchback is
enabled (SWB = 1), the high-frequency clock source is
not turned off (see the PMME bit description for more
information). Note that debug mode does not work with
PMM2 mode since switchback does not occur fast
enough to guarantee proper operation.
The MAXQ3108 incorporates power-management fea-
tures that support low-power operation with three
power-saving modes. Features include startup timer,
internal FLL oscillator, and switchback function.
The MAXQ3108 was developed for low-power applica-
tions and has three different levels of power-saving
Frequency-Locked Loop (FLL)
Power Conservation