MAXQ3108 Maxim Integrated Products, MAXQ3108 Datasheet - Page 43

• Manufacturer Part Number: MAXQ3108
• Description: Dual-Core Microcontroller
• Manufacturer: Maxim Integrated Products

www.DataSheet4U.com
I2CST.1: I2CTXI
I2CST.2: I2CRXI
I2CST.3: I2CSTRI
I2CST.4: I2CTOI
I2CST.5: I2CAMI
I2CST.6: I2CALI
I2CST.7: I2CNACKI
I2CST.8: I2CGCI
I2CST.9: I2CROI
I2CST.10: I2CSCL
I2CST.11: I2CSPI
I2CST.[13:12]: Reserved
I2CST.14: I2CBUSY
I2CST.15: I2CBUS
______________________________________________________________________________________
Low-Power, Dual-Core Microcontroller
I
successfully shifted out and the I
(NACK or ACK). This bit must be cleared by software once set. Setting this bit to 1 by software
causes an interrupt if enabled.
I
buffer. This bit must be cleared by software once set. Setting this bit to 1 by hardware causes an
interrupt if enabled. This bit is set by hardware only.
I
stretching enabled and is holding the SCL clock signal low. The I
this bit has been cleared to 0. Setting this bit to 1 by hardware causes an interrupt if enabled. This
bit must be cleared to 0 by software once set. This bit is set by hardware only.
I
condition or the I
happens when the I
using the bus or holding SCL low for an extended period of time. This bit must be cleared to 0 by
software once set. Setting this bit to 1 by software causes an interrupt if enabled.
I
address that matches the contents in its slave address register (I2CSLA) during the address stage.
This bit must be cleared to 0 by software once set. Setting this bit to 1 by software causes an
interrupt if enabled.
I
the arbitration. When the master loses arbitration, the I2CMST bit is cleared to 0. Setting this bit to 1
by hardware causes an interrupt if enabled. This bit must be cleared to 0 by software once set.
This bit is set by hardware only.
I
receiver. Setting this bit to 1 by hardware causes an interrupt if enabled. This bit must be cleared to
0 by software once set. This bit is set by hardware only.
I
and the general call address is received. This bit must be cleared to 0 by software once set.
Setting this bit to 1 by software causes an interrupt if enabled.
I
the receiver has already received two bytes since the last CPU read. This bit is cleared to 0 by
software reading the I2CBUF. Setting this bit to 1 by software causes an interrupt if enabled. Writing
0 to this bit does not clear the interrupt.
I
at a logic-high (1), and cleared to 0 when SCL is at a logic-low (0). This bit is controlled by
hardware and is read-only.
I
cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.
Reserved. Reads return 0.
I
when the I
the bus. This bit is controlled by hardware and is read only.
I
cleared to 0 when the STOP condition is detected. This bit is reset to 0 on all forms of reset and
when I2CEN = 0. This bit is controlled by hardware and is read-only.
2
2
2
2
2
2
2
2
2
2
2
2
2
C STOP Interrupt Flag. This bit is set to 1 when a STOP condition (P) is detected. This bit must be
C Transmit Complete Interrupt Flag. This bit indicates that an address or a data byte has been
C Receive Ready Interrupt Flag. This bit indicates that a data byte has been received in the I
C Clock Stretch Interrupt Flag. This bit indicates that the I
C Timeout Interrupt Flag. This bit is set to 1 if either the I
C Slave Address Match Interrupt Flag. This bit is set to 1 when the I
C Arbitration Loss Flag. This bit is set to 1 when the I
C NACK Interrupt Flag. This bit is set to 1 if the I
C General Call Interrupt Flag. This bit is set to 1 when the general call is enabled (I2CGCEN = 1)
C Receiver Overrun Flag. This bit indicates a receive overrun when set to 1. This bit is set to 1 if
C SCL Status. This bit reflects the logic state of the SCL signal. This bit is set to 1 when SCL is
C Busy. This bit is used to indicate the current status of the I
C Bus Busy. This bit is set to 1 when a START/REPEATED START condition is detected and
Special Function Register Bit Descriptions (continued)
2
C controller is actively participating in a transaction or when it does not have control of
2
C SCL low time has expired the timeout value specified in I2CTO register. This
2
C controller is operating in master mode and some other device on the bus is
2
C controller has received an acknowledgment from the receiver
2
C transmitter receives a NACK from the
2
C is configured as a master and loses in
2
C controller cannot generate a START
2
C controller is operating with clock
2
C module. The I2CBUSY is set to 1
2
C controller releases SCL after
2
C controller receives an
2
C
43