P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 94

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
8.2 Reset
The boundary-scan interface includes a state-machine controller (the TAP controller). In order to force the
TAP controller into the correct state after power-up of the device, a reset pulse must be applied to the
nTRST pin. If the boundary scan interface is to be used, then nTRST must be driven LOW, and then HIGH
again. If the boundary scan interface is not to be used, then the nTRST pin may be tied permanently LOW.
Note that a clock on TCK is not necessary to reset the device.
The action of reset (either a pulse or a DC level) is as follows:
8.3 Pullup Resistors
TDI, TMS, nTRST and TCK all have on-chip pullup resistors.
8.4 Instruction Register
The instruction register is 4 bits in length.
There is no parity bit. The fixed value loaded into the instruction register during the CAPTURE-IR
controller state is: 0001.
8.5 Public Instructions
The following public instructions are supported:
In the descriptions that follow, TDI and TMS are sampled on the rising edge of TCK and all output
transitions on TDO occur as a result of the falling edge of TCK .
8.5.1 EXTEST (0000)
The BS (boundary-scan) register is placed in test mode by the EXTEST instruction.
90
System mode is selected (i.e. the boundary scan chain does NOT intercept any of the signals passing
between the pads and the core).
IDcode mode is selected. If TMS and TCK are used to put the TAP controller in Shift-DR mode (see
Fig 32), the IDcode will be clocked out of TDO .
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
CLAMPZ
INTEST
IDCODE
BYPASS
Binary Code
0000
0011
0101
0111
1001
1100
1110
1111