P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 90
P60ARM-B
Manufacturer Part Number
P60ARM-B
Description
32-bit RISC microprocessor
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.P60ARM-B.pdf
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P60ARM-B
7.13 Coprocessor register transfer (Load from coprocessor)
Here the busy-wait cycles are much as above, but the transfer is limited to one data word, and ARM60 puts
the word into the destination register in the third cycle. The third cycle may be merged with the following
prefetch cycle into one memory N-cycle as with all ARM60 register load instructions. The cycle timings are
shown in Table 19: Coprocessor register transfer (Load from coprocessor).
7.14 Coprocessor register transfer (Store to coprocessor)
As for the load from coprocessor, except that the last cycle is omitted. The cycle timings are shown below
in Table 20: Coprocessor register transfer (Store to coprocessor).
86
not ready
ready
Cycle
n+1
n+2
1
2
3
1
2
n
•
Table 19: Coprocessor register transfer (Load from coprocessor)
Address
pc+8
pc+12
pc+12
pc+12
pc+8
pc+8
pc+8
pc+8
pc+12
pc+12
pc+12
nBW
1
1
1
1
1
1
1
1
1
nRW
0
0
0
0
0
0
0
0
0
CPdata
CPdata
CPdata
(pc+8)
(pc+8)
Data
-
-
-
-
nMREQ
1
1
0
1
1
1
1
1
0
SEQ
1
0
1
0
0
0
1
0
1
nOPC
0
1
1
0
1
1
1
1
1
nCPI
0
1
1
0
0
0
0
1
1
CPA
0
1
0
0
0
0
1
-
-
CPB
0
1
1
1
1
0
1
-
-
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