P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 9

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

2.0 Signal Description
A[31:0]
ABE
ABORT
ALE
BIGEND
CPA
CPB
D[31:0]
DATA32
Name
Type
OS8
OS8
I/
I
I
I
I
I
I
I
Addresses. This is the processor address bus. If ALE (address latch enable) is HIGH, the
addresses become valid during phase 2 of the cycle before the one to which they refer and
remain so during phase 1 of the referenced cycle. Their stable period may be controlled by
ALE as described below. Refer to section "AC parameters" for timing diagrams.
Address bus enable. This is an input signal which, when LOW, puts the address bus drivers
into a high impedance state. ABE must be tied HIGH when there is no system requirement
to turn off the address drivers.
Memory ABORT . This is an input which allows the memory system to tell the processor that
a requested access is not allowed. ARM60 can be configured to accept either early aborts for
compatibility with earlier processors or late aborts for greater flexibility.
Address latch enable. This input is used to control transparent latches on the address outputs.
Normally the addresses change during phase 2 to the value required during the next cycle,
but for direct interfacing to ROMs they are required to be stable to the end of phase 2. Taking
ALE LOW until the end of phase 2 will ensure that this happens. If the system does not
require address lines to be held in this way, ALE must be tied HIGH. The address latch is
static, so ALE may be held LOW for long periods to freeze addresses.
Big Endian configuration. When this signal is HIGH the processor treats bytes in memory as
being in Big Endian format. When it is LOW memory is treated as Little Endian.
Coprocessor absent. A coprocessor which is capable of performing the operation that ARM60
is requesting (by asserting nCPI ) should take CPA LOW immediately. If CPA is HIGH at the
end of phase 1 of the cycle in which nCPI went LOW, ARM60 will abort the coprocessor
handshake and take the undefined instruction trap. If CPA is LOW and remains LOW,
ARM60 will busy-wait until CPB is LOW and then complete the coprocessor instruction.
Coprocessor busy. A coprocessor which is capable of performing the operation which
ARM60 is requesting (by asserting nCPI ), but cannot commit to starting it immediately,
should indicate this by driving CPB HIGH. When the coprocessor is ready to start it should
take CPB LOW. ARM60 samples CPB at the end of phase 1 of each cycle in which nCPI is
LOW.
Data Bus. These are bidirectional signal paths which are used for data transfers between the
processor and external memory. During read cycles (when nRW is LOW), the input data
must be valid before the end of phase 2 of the transfer cycle. During write cycles (when nRW
is HIGH), the output data will become valid during phase 1 and remain valid throughout
phase 2 of the transfer cycle.
32 bit Data configuration. When this signal is HIGH the processor can access data in a 32 bit
address space using address lines A[31:0] . When it is LOW the processor can access data from
a 26 bit address space using A[25:0] . In this latter configuration the address lines A[31:26] are
not used. Before changing DATA32 , ensure that the processor is not about to access an
address greater that 0x3FFFFFF in the next cycle.
Table 1: Signal Description
Description
Signal Description
5